Well mask for CMOS process

Details Well mask for CMOS process Well mask for CMOS process

1985-07-22

1987-12-15

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 20, 437 27, 437 28, 437 30, 437 34, 437 56, 437933, 357 42, 357 90, H01L 754, H01L 21265

Patent

active

047133295

ABSTRACT:
A method of forming CMOS transistors with self-aligned field regions. First and second spaced apart areas are provided on a silicon substrate. A masking member is formed protecting the first of said areas and exposing the second. The exposed area is doped with a p-type material which is driven in to form a p-well. The same region is again doped with additional p-type material after which the CMOS transistors are fabricated.

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