Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2007-03-13
2007-03-13
Dang, Phuc T. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S291000
Reexamination Certificate
active
11025960
ABSTRACT:
A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.
REFERENCES:
patent: 5877049 (1999-03-01), Liu et al.
patent: 6306676 (2001-10-01), Stevens et al.
patent: 6326219 (2001-12-01), Markle et al.
patent: 6690423 (2004-02-01), Nakamura et al.
patent: 6744084 (2004-06-01), Fossum
patent: 6768149 (2004-07-01), Mann et al.
patent: 6777662 (2004-08-01), Drowley et al.
patent: 6794281 (2004-09-01), Madhukar et al.
patent: 2004/0232456 (2004-11-01), Hong
Mauritzson Richard A.
Patrick Inna
Rhodes Howard E.
Dang Phuc T.
Dickstein & Shapiro LLP
Micro)n Technology, Inc.
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