Well bias control circuit

Details Well bias control circuit Well bias control circuit

2002-10-31

2003-11-25

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06653890

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device having a PN Vt balance compensation circuit for compensating a threshold voltage difference between a PMOS transistor and an NMOS transistor and capable of operating with even a decreased power supply voltage while maintaining an optimum operation state. In recent years, as portable information terminals became widespread, further reduction in power is required for a CMOS LSI, and reduction in a power supply voltage, which is the most effective for power reduction, is being progressed. However, with a lower power supply voltage, variation in performance of a circuit according to processes and due to temperature change increases. An example of a technique of compensating such variations in performance of a circuit is, for example, as disclosed in Japanese Unexamined Patent Application No. 2001-156261 by the inventors herein, a technique of detecting operation speed of a main circuit and controlling a body bias so as to maintain the operation speed at a desired performance. The operation speed compensation is realized by detecting the operation speed of a main circuit by a delay monitor simulating a critical path of the main circuit, controlling a body bias of the delay monitor so as to maintain the operation speed of the delay monitor almost constant synchronously with input clocks, and applying the body bias also to the main circuit. In the Japanese Unexamined Patent Application No. 2001-156261, it is expressed as a technique of controlling the body bias. Substantially, the technique is to control biases of an N well and a P well for constructing a PMOS transistor and an NMOS transistor. In the following, in the invention, it will be described as the technique of controlling the bias of each of the N well and the P well for constructing a PMOS transistor and an NMOS transistor.
SUMMARY OF THE INVENTION
When the performance of a transistor varies according to a fabricating process and a difference occurs between a threshold voltage of a PMOS transistor and a threshold voltage of an NMOS transistor, even if the circuit speed is the same, leakage currents of the circuits may differ from each other. This happens for the reason that the leakage current depends on, not the circuit operation speed, but a threshold voltage of a transistor. In the technique, the body bias is controlled to maintain the operation speed, so that the circuit speed can be compensated. However, when the threshold voltage varies, the leakage current cannot be compensated. If decrease in the voltage is further advanced and the threshold voltage of a transistor decreases in future, the variations in the threshold voltage become conspicuous. As a result, the leakage current increases, and the ratio of the power consumption corresponding to the leakage current in the power consumption of the circuit increases. Consequently, compensation of the leakage current is an important technique.
According to the invention, as a well bias control circuit for compensating the threshold voltage difference between a PMOS transistor and an NMOS transistor, in a part of the region of a main circuit constructed by a CMOS, a control circuit simulating a critical path of the main circuit constructed by the CMOS and including a delay monitor for monitoring a delay in the path is formed in a process of forming the main circuit. The control circuit is provided with a PN Vt balance compensation circuit for compensating an output of the delay monitor in accordance with the threshold voltage difference between the PMOS and NMOS transistors, thereby compensating the circuit speed by monitoring the delay of the path and compensating the threshold voltage difference between the PMOS and NMOS transistors by the PN Vt balance compensation circuit.


REFERENCES:
patent: 5883544 (1999-03-01), So et al.
patent: 6466077 (2002-10-01), Miyazaki et al.
patent: 6518825 (2003-02-01), Miyazaki et al.
patent: 2001/0048319 (2001-12-01), Miyzazaki et al.
patent: 2001-156261 (2000-04-01), None

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