Well bias circuit in a memory device and method of operating...

Details Well bias circuit in a memory device and method of operating... Well bias circuit in a memory device and method of operating...

2007-06-10

2009-06-09

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290, C365S185250

Reexamination Certificate

active

07545676

ABSTRACT:
A well bias circuit in a memory device includes a well voltage supplying circuit configured to apply a high voltage to a well for erasing data in a memory cell. A well discharging circuit is configured to discharge the high voltage applied to the well in accordance with a first control signal after the data in the memory cell is erased. A well-to-ground circuit is configured to control the well bias to obtain a ground voltage in accordance with a second control signal. A control circuit is configured to activate the well discharging circuit for a predetermined time when power is turned on.

REFERENCES:
patent: 6031774 (2000-02-01), Chung
patent: 7224624 (2007-05-01), Lee et al.
patent: 1020000002889 (2000-01-01), None
patent: 100481841 (2005-03-01), None

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