Weighted throttling mechanism with rank based throttling for...

Static information storage and retrieval – Powering

Reexamination Certificate

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Details

C365S189070

Reexamination Certificate

active

06507530

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to control of a memory system. More particularly, the present invention relates to the throttling of a dynamic random access memory (DRAM) based subsystem of computing platforms.
2. Discussion of the Related Art
As the peak bandwidth capabilities of a memory subsystem (such as a DRAM memory device) increase, there is a greater potential to damage the components of the memory subsystem through thermal overstress. If the heat generated by the memory device is not removed properly, the internal temperature of the memory device will rise beyond the maximum tolerated by the device and the device will eventually fail. The increased potential for thermal overstress is a direct consequence of the increased rate not only of data transfer, but that of command and address transfers as well. This situation necessitates a method of preventing such damage to the various entities forming a memory subsystem, which may include a memory controller and DRAM components. The thermal time constants of the components forming the memory subsystem are on the order of seconds, and therefore, the “activity” level or rate of the memory subsystem must be maintained over some period of time (e.g., greater than 100 milliseconds) in order to possibly foster a thermal overstress event.
One way to prevent damage via thermal overstress is to detect when the activity rate in a memory subsystem has been at a potentially damaging level for a period of time. Then, the rate of access to the memory subsystem may be throttled back (i.e., scaled back) to a level that prevents the thermal overstress.
This throttling scheme has been implemented in previous memory systems. However, it is simplistic in its implementation. In other words, throttling in the prior art is based only on the aggregate data transfer rates sustained over a period of time. This throttling methodology has some serious flaws. For example, it considers the memory subsystem as an indivisible entity, which may be an erroneous assumption. In many systems, multiple partitions of memory exist, and not all partitions are active simultaneously. Secondly, prior throttling methodology does not account for all of the commands sent to the memory subsystem. Finally, the prior art throttling methodology fails to acknowledge the fact that different commands have different power consumption rates, and thus lead to different thermal results. These deficiencies often lead to the necessity to overcompensate by over-throttling the memory subsystem in order to maintain a reasonable margin of safety.
Accordingly, there is a need for a system and method of throttling to enable more precise control over the memory subsystem, and to alleviate the necessity to over-throttle in order to provide optimum performance versus thermal overstress protection.


REFERENCES:
patent: 5602790 (1997-02-01), Mullarkey
patent: 5801982 (1998-09-01), Blodgett
patent: 5875142 (1999-02-01), Chevallier
patent: 5898343 (1999-04-01), Morgan
patent: 5903506 (1999-05-01), Blodgett
patent: 5963103 (1999-10-01), Blodgett
patent: 6021076 (2000-02-01), Woo
patent: 6262749 (2001-07-01), Finger et al.
patent: 6300961 (2001-10-01), Finger et al.
patent: 6317364 (2001-11-01), Guterman et al.

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