Weighted fair queue serving plural output ports

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

Reexamination Certificate

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C370S412000

Reexamination Certificate

active

07929548

ABSTRACT:
A data communication apparatus includes a plurality of output ports and a scheduler for assigning priorities for outbound data frames. The scheduler includes one or more scheduling queues. Each scheduling queue indicates an order in which data flows are to be serviced. At least one scheduling queue has a respective plurality of output ports assigned to the scheduling queue. That is, the scheduling queue is shared by two or more output ports.

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Abstract of Publication entitled “Design of packet-fair queuing schedulers using a RAM-based search engine” by JH Chao et al, IEEE Journal of Selected Areas in Communications, vol. 17, No. 6, pp. 1105-1126, Jun. 1999.
Lyons et al., “Estimating Clock Speeds for the ATMSWITCH Architecture”, Proc. NETWORKS '99 (The Third New Zealand ATM and Broadband Workshop), Jan. 21-22, 1999, pp. 39-53.

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