Weighted erasure codec for the (24, 12) extended Golay code

Details Weighted erasure codec for the (24, 12) extended Golay code Weighted erasure codec for the (24, 12) extended Golay code

1981-01-30

1983-08-02

Atkinson, Charles E.

Excavating

371 5, 371 41, G06F 1110

Patent

active

043970222

ABSTRACT:
A codec consists of an encoder and decoder. The encoder provides 12 information bits, 11 parity bits generated according to the polynomial for the (23, 12) Golay code, and an overall parity bit to a transmitter at selected transmit times to form a 24-bit block of data. The decoder is separated into two independent list decoders, a comparator, and common clock generator and output buffers. Each list decoder is divided into a syndrome generator and an overall parity check generator, a syndrome error pattern table, an input buffer, error correction logic, and four-error detection logic. The error pattern table includes a pair of read only memories storing the most likely 12-bit error patterns at each ROM address corresponding to each syndrome. An additional 4-bit output is used to indicate the number of errors in the associated error pattern. The comparator compares the number of errors detected in the two independent decoders and chooses the decoder having the fewer number of errors to provide the corrected data.

REFERENCES:
patent: 3078443 (1963-02-01), Rose
patent: 4117458 (1978-09-01), Burghard et al.
patent: 4168486 (1979-09-01), Leygory
Mears, Jr., High-Speed Error Correcting Encoder/Decoder, IBM Technical Disclosure Bulletin, vol. 23, No. 4, Oct. 1980, pp. 2135-2136.
Peterson & Weldon, Error Correcting Codes, The MIT Press, 1972, pp. 120-121, 210.
Lin, An Introduction to Error-Correcting Codes, Prentice-Hall, 1970, pp. 101-109.

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