Weighted-delay column adder and method of organizing same

Details Weighted-delay column adder and method of organizing same Weighted-delay column adder and method of organizing same

1990-02-14

1992-11-03

Mai, Tan V.

Boots, shoes, and leggings

G06F 750

Patent

active

051611198

ABSTRACT:
An adder array for adding two or more input addends, whose bit lengths are not necessarily matched, and a method of configuring the adder array are disclosed. The addends are organized according to bit weight, and bits of equal weight are added in adder columns. Carry-outs are introduced into subsequent, higher weight adder columns according to delay. Thereby, the delay associated with the addition of the addends is minimized. Method and apparatus is disclosed.

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