Weight multiplier for use in an adapter processor

Details Weight multiplier for use in an adapter processor Weight multiplier for use in an adapter processor

1976-08-31

1977-12-20

Ruggiero, Joseph F.

Boots, shoes, and leggings

333 18, 364825, H04B 304, G06G 716

Patent

active

040644227

ABSTRACT:
A weight multiplier for use in an adaptive processor. The input signal from a tapped delay line is split in a 3 dB hybrid into two equal level and equal phase signals. Each signal is fed to a mixer together with a signal performing the function of an oscillator signal. Output signals from the mixer are subtracted in a broadband hybrid. The result of this subtractor is then fed to a summer to supply a loop feedback signal.

REFERENCES:
patent: 3081434 (1963-03-01), Sandberg
patent: 3375473 (1968-03-01), Lucky
patent: 3521041 (1970-07-01), Van Blerkom et al.
patent: 3597541 (1971-08-01), Proakis
patent: 3758881 (1973-09-01), Rummler

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