Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor
Reexamination Certificate
2002-10-30
2003-10-28
Dinkins, Anthony (Department: 2831)
Electricity: electrical systems and devices
Electrostatic capacitors
Fixed capacitor
C361S306100, C361S305000, C257S303000, C257S309000, C257S310000
Reexamination Certificate
active
06639784
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to capacitors utilized in integrated circuits and, in particular, to a wedge-shaped capacitor design that utilizes interdigitated conductive layers to form a high density capacitor with only one additional mask.
BACKGROUND OF THE INVENTION
Capacitors are commonly utilized in integrated circuits. As shown in
FIG. 1
, a conventional poly-poly dual plate capacitor
10
includes two overlapping polysilicon plates, i.e. an upper poly plate
12
and a lower poly plate
14
, separated by a layer of dielectric material
16
, typically silicon dioxide. Capacitance Cpp is the capacitance formed between the upper plate
12
and the lower plate
14
. The lower poly plate
14
is separated from the underlying silicon substrate
18
by a layer of dielectric material
20
, also typically silicon dioxide. The bottom plate forms a parasitic capacitance Cps with the substrate
18
. As further shown in
FIG. 1
, an electrically charged well
22
is typically formed beneath the capacitor structure to prevent the coupling of signals to the substrate
18
, thereby reducing the effective value of the parasitic capacitance Cps. As is well known, the well
22
must be reverse-biased in order to create a depletion region around the well-substrate junction.
The main disadvantage of all integrated capacitors, including poly-poly capacitors, is a relatively small capacitance Cpp per unit area that requires large expensive devices for even modest capacitance values. An additional problem of dual plate capacitors structures is the above-described unwanted parasitic capacitance Cps between the lower poly plate and the underlying silicon substrate that can affect circuit performance and couple noise to and from the substrate.
SUMMARY OF THE INVENTION
The present invention provides an interdigitated capacitor structure that is formed in a wedge-shaped trench. Alternating layers of insulating material and conductive material are formed in the trench such that each layer of conductive material in the trench is electrically isolated from adjacent layers of conductive material. A first electrical contact is formed to electrically link in parallel a first set of alternating layers of conductive material formed in the trench. A second electrical contact is formed to electrically link in parallel a second set of alternating layers of conductive material formed in the trench. The two sets of inter-linked layers of conductive material define the interdigitated capacitor structure.
The capacitor structure of the present invention can be fabricated within either the front end of the process. For example, the trench can etched into silicon, preferably during the deep or shallow trench etch stage of the process. Alternatively, the capacitor trench can be etched as an additional trench, for example into the inter layer dielectric (IDL) as part of the back end processing flow. The structure can be designed geometrically to provide maximum capacitance per unit area using only one additional mask. The structure is not coupled to the substrate, thereby eliminating the noise related with conventional capacitor structures.
The features and advantages of the present invention will be more fully appreciated upon consideration of the following detailed description and the accompanying drawings which set forth in illustrative embodiment in which the principles of the invention are utilized.
REFERENCES:
patent: 4810669 (1989-03-01), Kobayashi
patent: 5317432 (1994-05-01), Ino
patent: 5394000 (1995-02-01), Ellul et al.
patent: 5952687 (1999-09-01), Kawakubo et al.
patent: 6215646 (2001-04-01), Ochiai et al.
patent: 6437387 (2002-08-01), Gutsche
Hopper Peter
Hwang Kyuwoon
Lindorfer Philipp
Strachan Andy
Vashchenko Vladislav
Dinkins Anthony
National Semiconductor Corporation
Stallman & Pollock LLP
LandOfFree
Wedge-shaped high density capacitor and method of making the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Wedge-shaped high density capacitor and method of making the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wedge-shaped high density capacitor and method of making the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3166539