Abrading – Abrading process – Utilizing fluent abradant
Reexamination Certificate
1999-06-21
2002-03-19
Eley, Timothy V. (Department: 3723)
Abrading
Abrading process
Utilizing fluent abradant
C451S041000, C451S053000, C451S449000, C451S488000, C451S550000
Reexamination Certificate
active
06358119
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more specifically to a method and apparatus to eliminate copper line damage after copper line Chemical Mechanical Polishing.
(2) Description of the Prior Art
The use of copper has become increasingly more important for the creation of multilevel interconnections in semiconductor circuits, however copper lines frequently show damage after CMP and clean. This damage of copper lines causes planarization problems of subsequent layers that are deposited over the copper lines because these layers may now be deposited on a surface of poor planarity. Particularly susceptible to damage are isolated copper lines or copper lines that are adjacent to open fields. While the root causes for these damages are at this time not clearly understood, poor copper gap fill together with subsequent problems of etching and planarization are suspected. Where over-polish is required, the problem of damaged copper lines becomes even more severe. The present invention teaches methods for avoiding the observed phenomenon of damaged copper lines.
Recent applications have successfully used copper as a conducting metal line, most notably in the construct of CMOS 6-layer copper metal devices. Even for these applications however, a wolfram plug was still used for contact points in order to avoid damage to the devices.
The reliability of a metal interconnect is most commonly described by a lifetime experiment on a set of lines to obtain the medium time to failure. The stress experiment involves stressing the lines at high current densities and at elevated temperatures. The failure criterion is typically an electrical open for non-barrier conductors or a predetermined increase in line resistance for barrier metalization.
The mean time to failure is dependent on the line geometry where this failure is directly proportional to the line width and the line thickness. Experimentally, it has been shown that the width dependence is a function of the ratio of the grain size d of the film and the width of the conductor w. As the ratio w/d decreases, the mean time to failure will increase due to the bamboo effect.
Conventional methods proposed for placing copper conductors on silicon based substrates are based on the deposition of a variety of layers where each layer has characteristics of performance or deposition that enhance the use of copper as the major component within conducting lines. This approach has met with only limited success and has as yet not resulted in the large-scale adaptation of copper.
U.S. Pat. No. 5,187,119 teaches that, in the field of high density interconnect technology, many integrated circuit chips are physically and electrically connected to a single substrate. To achieve a high wiring and packing density, it is necessary to fabricate a multilayer structure on the substrate to connect integrated circuits to one another. Embedded in other dielectric layers are metal conductor lines with vias (holes) providing electrical connections between signal lines or to the metal power and ground planes. Adjacent layers are ordinarily formed so that the primary signal propagation directions are orthogonal to each other. Since the conductor features are typically narrow in width and thick in a vertical direction (in the range of 5 to 10 microns thick) and must be patterned with microlithography, it is important to produce patterned layers that are substantially flat and smooth (i.e., planar) to serve as the base for the next layer.
Two common techniques used to achieve planarity on a semiconductor surface are a Spin-On-Glass (SOG) etchback process and a Chemical Mechanical Polishing (CMP) process. Although both processes improve planarity on the surface of a semiconductor wafer, CMP has been shown to have a higher level of success in improving global planarity. The assurance of planarity is crucial to the lithography process, as the depth of focus of the lithography process is often inadequate for surfaces which do not have a consistent height.
U.S. Pat. No. 5,187,119 further teaches that, if the surface is not flat and smooth, many fabrication problems occur. In a multilayer structure, a flat surface is extremely important to maintain uniform processing parameters from layer to layer. A non-flat surface results in photoresist thickness variations that require pattern or layer dependent processing conditions. The layer dependent processing greatly increases the problem complexity and leads to line width variation and reduced yield. Thus, in fabricating multilayer structures, maintaining a flat surface after fabricating each layer allows uniform layer-to-layer processing.
A further critical consideration for obtaining high yields and suitable performance characteristics of semiconductor devices is that, during the fabrication process, the cleanliness of the silicon wafers is meticulously maintained. It is therefore important to, at all stages of the fabrication process, remove impurities from the surface of the wafer in order to prevent the diffusion of impurities into the semiconductor substrate during subsequent high-temperature processing. Some impurities are donor or acceptor dopants that directly affect device performance characteristics. Other impurities cause surface or bulk defects such as traps, stacking faults or dislocations. Surface contaminants such as organic matter, oil or grease lead to poor film adhesion. The various types of impurities and contaminants must be removed by careful cleaning, such as chemical or ultrasonic cleaning at initiation of silicon processing and in various appropriate steps during processing.
Chemical Mechanical Polishing is a method of polishing materials, such as semiconductor substrates, to a high degree of planarity and uniformity. The process is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry on the substrate. One typical chemical mechanical polishing process uses a large polishing pad that is located on a rotating platen against which a substrate is positioned for polishing, and a positioning member which positions and biases the substrate on the rotating polishing pad. Chemical slurry, which may also include abrasive materials therein, is maintained on the polishing pad to modify the polishing characteristics of the polishing pad in order to enhance the polishing of the substrate.
A common requirement of all CMP processes is that the substrate be uniformly polished. In the case of polishing an electrical insulating layer, it is desirable to polish the layer uniformly from edge to edge on the substrate. To ensure that a planar surface is obtained, the electrically insulating layer must be uniformly removed. Uniform polishing can be difficult because several machine parameters can interact to create non-uniformity in the polishing process. For example, in the case of CMP, misalignment of the polishing wheel with respect to the polishing platen can create regions of non-uniform polishing across the diameter of the polished surface. Other machine parameters, such as non-homogeneous slurry compositions and variations in the platen pressure, can also create non-uniform polishing conditions.
U.S. Pat. No. 5,770,095 (Sasaki et al.) teaches Cu CMP methods that include low temperature CMP (temp ranges −2 degrees C. to 100 degrees C.) and various slurries that appear to include inhibitors. See cols. 5 13, examples 1 to 4.
FIG. 13
appears to show a chiller for a CMP platen, see col. 12, line 49.
U.S. Pat. No. 5,607,718 (Sasaki et al.) discloses a Cu CMP method at a low temperature (less than 15 degrees C.), see claims 2, 16, etc.
U.S. Pat. No. 5,840,629 (Carpio) shows a Cu CMP slurry composition including corrosion inhibitors, see col. 3, lines 21 to 30.
U.S. Pat. No. 5,300,155 (Sandu et al.) discloses a CMP method where a metal is CMP at different temperatures. This pate
Chen Ying-Ho
Jang Syun-Ming
Shih Tsu
Twu Jih-Churng
Ackerman Stephen B.
Eley Timothy V.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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