Waveform shaper for semiconductor testing devices

Details Waveform shaper for semiconductor testing devices Waveform shaper for semiconductor testing devices

1993-09-15

1995-04-11

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

371 27, 327100, 327294, G01R 3128

Patent

active

054061326

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE PRESENT INVENTION

The present invention relates to a waveform shaper for semiconductor testing devices and, more particularly, to a wave-form shaper for semiconductor devices which switches, in real time, the waveform mode that determines the driver waveform which is applied to a semiconductor to be tested.


DESCRIPTION OF THE RELATED ART

Referring first to a block diagram shown in FIG. 1, a conventional waveform shaper will be outlined. A waveform shaper 100 has built therein one waveform mode register 105, wherein a waveform mode is preset. The waveform mode register 105 has an 8-bit width and the meaning of each bit is such as given below in Table 1.


TABLE 1 ______________________________________ Meaning of Each Bit of waveform Mode Register Name Meaning ______________________________________ SEL A This means selecting clock A as a SET or RESET signal; the clock is selected as the RESET signal or SET signal, depending on whether pattern data from a pattern generator is a "0" or "1." SEL SET B This means selecting clock B as the SET signal; the clock is selected or not, depending on a whether the pattern data from the pattern generator is a "1" or "0." SEL RESET B This means selecting clock B as the RESET signal; the clock is selected or not, depending on whether the pattern data from the pattern generator is a "0" or "1." SEL SET C This means selecting clock C as the SET signal; the clock is selected or not, depending on whether the pattern data from the pattern generator is a "1" or "0." SEL RESET C This means selecting clock C as the RESET signal; the clock is selected or not, depending on whether the pattern data from the pattern generator is a "0" or "1." INV A This inverts the relationship between the pattern data and the selection of signals in SEL A. INV B This inverts the relationship between the pattern data and the selection of signals in SEL SET B and SEL RESET B. INV C This inverts the relationship between the pattern data and the selection of signals in SEL SET C and SEL RESET C. ______________________________________
A brief description of a conventional phase change circuit will be given, with reference to a block diagram of FIG. 2 and a timing chart of FIG. 3. A phase change circuit 101 is to changes pattern data, which is generated by a pattern generator 200 in FIG. 1, from the phase of an M clock signal (a clock signal synchronized with a pattern data cycle) MCK, which is available from a timing generator 300, to the phases respectively corresponding to A, B and C clock signals ACK. BCK and CCK which determine the edge timing of a waveform. The timing generator 300 generates clock pulses of the clock signals ACK, BCK and CCK in desired phases that correspond to respective cycles of the pattern data.
The phase change circuit 101 permits high-speed processing of the pattern data and makes the phase setting range for A, B and C clock signals ACK, BCK and CCK wider than the pattern data cycle period. The phase change circuit 101 changes the pattern data, which is entered from an input terminal Din, from the phase of the M clock signal MCK to the phases of the clock signals ACK, BCK and CCK and provides outputs to output terminals DA, DB and DC. As is well-known in the art, when the pattern data from the pattern generator 200 is input into the phase change circuit, four NAND gates are opened one by one in a cyclic manner by a modulo 4 counter CO and a decoder DO upon each occurrence of the clock MCK, by which are generated four frequency-divided clocks shown FIG. 3, Rows, C, D, E and F, and these clocks are provided to flip-flops F0 through F3, respectively. By this, pattern data shown in FIG. 3, Row A is converted into four parallel pieces of data each having a cycle length four times longer than the original data, as depicted on Rows G, H, I and J.
Supplied with the count value of a modulo 4 counter C1 which counts the clock ACK, a decoder D1 provides output signals (FIG. 3, Rows L, M, N and O) to

REFERENCES:
patent: 4635096 (1987-01-01), Morgan
patent: 4788684 (1988-11-01), Kawaguchi et al.
patent: 5003194 (1991-03-01), Engelhard
patent: 5170398 (1992-12-01), Fujieda et al.

Affiliated with

Also associated with

Rating

Waveform shaper for semiconductor testing devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Waveform shaper for semiconductor testing devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Waveform shaper for semiconductor testing devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1540627