Watchdog timer having a reset detection circuit

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371 62, G06F 1108

Patent

active

047962119

ABSTRACT:
In a watchdog timer comprising a reset data detection circuit for detecting input reset data and outputting a reset signal, and a first counter that outputs a carry signal unless, before its count overflows, it receives a reset signal from said reset data detection circuit, the rest data detection circuit comprises a latch circuit for latching said reset data, a second couner for counting the number of times a said reset signal is generated, and a comparator for comparing the output data from the latch circuit and the second counter and outputting the reset signal when the output data from the latch circuit and the outputting the reset signal match.

REFERENCES:
patent: 4618953 (1986-10-01), Daniels et al.
patent: 4627057 (1986-12-01), Schmidt et al.
patent: 4701758 (1987-10-01), Dunkerton et al.
patent: 4705970 (1987-11-01), Turnpaugh

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