Watchdog timer

Details Watchdog timer Watchdog timer

1986-07-03

1988-08-09

Heckler, Thomas M.

Boots, shoes, and leggings

371 62, G06F 922, G06F 1128

Patent

active

047632968

ABSTRACT:
A data processor (2) including a watchdog timer (8) comprising: a first memory (4) holding a primary operating routine for cyclic execution during operation of the data processor, an address bus (6) for addressing locations in said first memory means, a timer (10) for continuous operation during operation of the data processor and for effecting a system reset in response to the timer reaching a predetermined value, the primary operating routine including at at least one predetermined location an instruction to reset the timer, whereby in normal operation of the data processor the timer does not reach the predetermined value, wherein the data processor further includes a second memory (12) for holding the address of the location containing the instruction to reset the timer, and a comparator (16) coupled to the address bus and the timer for preventing the timer from being reset in response to an instruction to reset the timer unless the address on the address bus is held in the second memory.

REFERENCES:
patent: 4099255 (1978-07-01), Stanley et al.
patent: 4118792 (1978-10-01), Struger et al.
patent: 4263647 (1981-04-01), Merrell et al.
patent: 4538273 (1985-08-01), Lasser
patent: 4586179 (1986-04-01), Sirazi et al.
patent: 4594685 (1986-06-01), Owens
patent: 4627060 (1986-12-01), Huang et al.

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