Warpage resistant semiconductor package and method for...

Details Warpage resistant semiconductor package and method for... Warpage resistant semiconductor package and method for...

2011-08-02

2011-08-02

Tran, Long K (Department: 2829)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S033000, C438S109000, C257SE21499, C257SE23064, C257SE23067, C257SE23085, C257SE23180, C257SE23190

Reexamination Certificate

active

07989264

ABSTRACT:
A semiconductor package and a method for manufacturing the same is provided for minimizing or preventing warpage and twisting of semiconductor chip bodies as a result of thinning them during gringing. The semiconductor package includes a semiconductor chip body and a substrate. The semiconductor chip body has a first surface, a second surface facing away from the first surface, through-electrodes which pass through the semiconductor chip body and project from the second surface, and a warpage prevention part which projects in the shape of a fence along an edge of the second surface. The substrate has a substrate body and connection pads which are formed on an upper surface of the substrate body, facing the second surface, and which are connected with the projecting through-electrodes.

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patent: 2007/0210447 (2007-09-01), Kinsley
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USPTO Office Action mailed Feb. 17, 2010 for U.S. Appl. No. 12/044,420.
USPTO Notice of Allowance mailed Jun. 1, 2010 for U.S. Appl. No. 12/044,420.

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