Fishing – trapping – and vermin destroying
Patent
1994-03-04
1994-11-29
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437211, 437214, 437215, 437217, 437219, H01L 2160
Patent
active
053690583
ABSTRACT:
The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lower major surfaces of the integrated circuit package. To prevent the resulting ultra-thin integrated circuit package from warping, a thin layer of material with a coefficient of thermal expansion less than that of silicon is mounted to the upper major surface of the package after some of the casing material has been removed uniformly from the upper major surface. Also, a thin layer of material with a coefficient of thermal expansion greater than that of silicon may be mounted to the lower major surface of the package after some of the casing material has been removed uniformly from the lower major surface and after a layer of adhesive has been applied to the thin layer of material and cured. The result is an ultra-thin integrated circuit package that is thermally and mechanically balanced to prevent warping.
REFERENCES:
patent: 2241493 (1960-12-01), Andrulits et al.
patent: 3436604 (1966-04-01), Hyltin et al.
patent: 3614546 (1971-10-01), Avins
patent: 3713893 (1973-01-01), Shirland
patent: 3739462 (1973-06-01), Hasty
patent: 4103318 (1978-07-01), Schwede
patent: 4158745 (1979-06-01), Keller
patent: 4288841 (1981-09-01), Gogal
patent: 4321418 (1982-03-01), Dran et al.
patent: 4437235 (1984-03-01), McIver
patent: 4451973 (1984-06-01), Tatano et al.
patent: 4521828 (1985-06-01), Fanning
patent: 4525921 (1985-07-01), Carson et al.
patent: 4530152 (1985-07-01), Roche et al.
patent: 4630172 (1986-12-01), Stenerson et al.
patent: 4633573 (1987-01-01), Scherer
patent: 4680617 (1987-07-01), Ross
patent: 4684975 (1987-08-01), Takiar et al.
patent: 4722060 (1988-01-01), Quinn et al.
patent: 4733461 (1988-03-01), Nakano
patent: 4763188 (1988-08-01), Johnson
patent: 4796078 (1989-01-01), Phelps, Jr. et al.
patent: 4821148 (1989-04-01), Kobayashi et al.
patent: 4823234 (1989-04-01), Konishi et al.
patent: 4829403 (1989-05-01), Harding
patent: 4833568 (1989-05-01), Berhold
patent: 4839717 (1989-06-01), Phy et al.
patent: 4855868 (1989-08-01), Harding
patent: 4862245 (1989-08-01), Pashby et al.
patent: 4862249 (1989-08-01), Carlson
patent: 4878106 (1989-10-01), Sachs
patent: 4884237 (1989-11-01), Mueller et al.
patent: 4891789 (1990-01-01), Quattrini et al.
patent: 4948645 (1990-08-01), Holzinger et al.
patent: 4953005 (1990-08-01), Carlson et al.
patent: 4953060 (1990-08-01), Lauffer et al.
patent: 4994411 (1991-02-01), Naito et al.
patent: 4997517 (1991-03-01), Parthasarathi
patent: 5014113 (1991-05-01), Casto
patent: 5016138 (1991-05-01), Woodman
patent: 5041015 (1991-08-01), Travis
patent: 5049527 (1991-09-01), Merrick et al.
patent: 5057906 (1991-10-01), Ishigami
patent: 5065277 (1991-11-01), Davidson
patent: 5086018 (1992-02-01), Conru et al.
patent: 5089876 (1992-02-01), Ishioka
patent: 5099393 (1992-03-01), Bentlage et al.
patent: 5108553 (1992-04-01), Foster et al.
patent: 5138430 (1992-08-01), Gow, 3rd. et al.
patent: 5138434 (1992-08-01), Wood et al.
patent: 5139430 (1992-08-01), Mori
patent: 5147822 (1992-09-01), Yamazaki et al.
patent: 5151559 (1992-09-01), Conru et al.
patent: 5155063 (1992-10-01), Tada
patent: 5214845 (1993-06-01), King et al.
patent: 5223739 (1993-06-01), Katsumata et al.
Information allegedly written by Emory Garth regarding "Memory Stacks", Applicant received a facsimile from Emory Garth on Jan. 26, 1993. (Publication date unknown).
Catalog of Dense-Pac Microsystems, Inc. describing two products: DPS512X16A3 Ceramic 512K X 16 CMOS SRAM Module and DPS512X16AA3 High Speed Ceramic 512K X 16 CMOS SRAM Module, pp. 865-870. (Publication date unknown).
Burns Carmen D.
Cady James W.
Roane Jerry M.
Troetschel Philip R.
Hearn Brian E.
Picardat Kevin M.
Staktek Corporation
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