Wallace-tree multipliers using half and full adders

Details Wallace-tree multipliers using half and full adders Wallace-tree multipliers using half and full adders

1997-02-28

2000-05-16

Ngo, Chuong Dinh

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708625, 708708, G06F 750

Patent

active

060650338

ABSTRACT:
An apparatus sums a plurality of columns of binary bits to produce a plurality of partial sum and carry bits. The bits of a particular column being of the same order of magnitude, and the bits of different columns differing in orders of magnitude. The apparatus includes one or more full adder. Each full adder receives three bits as an input to produce a first sum bit and a first carry bit as output. The apparatus also includes one or more half adders. Each half adder receives two bits as input to produce a second sum bit and a second carry bit as output. The full adders and half adder are interconnected as a plurality of interconnecting column adders. Each column adder sums bits of the input of at least one column and generates a partial sum and carry bit. Each column adder has a plurality of stages. A plurality of conductors interconnect the stages of each column adder with other stages in the same column adder and with stages in other adjacent column adders.

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