Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2003-06-23
2009-08-18
Kindred, Alford W (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S010000
Reexamination Certificate
active
07577823
ABSTRACT:
The present invention relates to a multi-processor computer system comprisingat least two processors for parallel execution of processes,at least two cache memory units, each being associated with and connected to a separate processor,a connection bus connecting said processors and said cache memory units, anda process list unit connected to said connection line for storing a process list of processes to be available for execution by said processors.In order to enable power saving if no processes for execution are available while guaranteeing a fast wake-up procedure if such processes are available it is proposed according to the present invention that said processors are adapted for loading a global wake-up variable signalling process additions of processes to said process list into their associated cache memory unit, for switching into a low-power mode if said process list contains no process for execution by said processors and for switching into a normal-power mode if said wake-up variable signals an addition of a process to said process list.Thus, according to the present invention the cache coherence protocol is used for communicating and signalling the availability of processes for execution.
REFERENCES:
patent: 4747041 (1988-05-01), Engel et al.
patent: 5182810 (1993-01-01), Bartling et al.
patent: 5754436 (1998-05-01), Walsh et al.
patent: 6158000 (2000-12-01), Collins
Geib Benjamin P
Kindred Alford W
NXP B.V.
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