Wait state mechanism for a high speed bus which allows the bus t

Details Wait state mechanism for a high speed bus which allows the bus t Wait state mechanism for a high speed bus which allows the bus t

1992-08-21

1994-08-16

Ray, Gopal C.

Boots, shoes, and leggings

364260, 364240, 3642402, 3642715, 3642405, 364DIG1, G06F 1338

Patent

active

053394402

ABSTRACT:
The present invention provides a protocol method for waiting the bus in a digital computer and an apparatus for implementing that protocol. By allowing the bus to continue running after a wait command has been asserted, modules on the computer bus are not required to respond instantly to the wait command. Information on the bus during the multiple cycles of the wait period is defined as invalid and valid data is driven on the bus after the wait period has expired. Bus driver modules are provided with a replay queue to replay, on the bus, data the driver module drove on the bus during the wait period if required.

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IBM Technical Dis. Bulletin, vol. 25, #7A, Dec. 1982, NY, US `Wait State Generator`.

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