Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2003-04-09
2004-07-06
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S707000, C438S706000, C438S710000
Reexamination Certificate
active
06759341
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to manufacture of semiconductor wafers (the process known as “wafering”). In particular, the present invention relates to use of plasma etching to improve the wafer's flatness and the thickness uniformity.
Manufacture of silicon wafers starts with growing a monocrystalline silicon ingot. After initial testing and grinding, the ingot is sawed into slices, and each slice is processed to obtain a uniformly thick wafer with smooth flat surfaces. Typical processing includes:
1. Lapping and grinding of the wafer to remove any saw marks left by the ingot sawing operation. This step also serves to increase the wafer flatness and the thickness uniformity.
2. A wet etch to remove the surface damage caused by the lapping and grinding.
3. After the wet etch, chemical mechanical polishing (CMP) of one or both surfaces or the wafer to produce a highly reflective, scratch and damage free surface suitable for photolithography.
See S. Wolf et al., “Silicon Processing for the VLSI Era”, vol. 1 (“Process Technology”), 1986, pages 23-26, which are incorporated herein by reference.
While the lapping, the grinding and the wet etch increase the overall flatness and thickness uniformity, these operations introduce non-uniformity near the wafer edges. Silicon is removed faster near the edges, which results in an “edge roll off”. See FIG.
1
. Wafer
110
is thinner near the edges, with the top surface
110
.
1
sloping down near the edges. (The edge roll off may also be present at the bottom surface of the wafer, this is not shown in
FIG. 1.
) If the roll off is high, a longer polishing operation (CMP) will be needed to reduce the roll off to an acceptable value. Since the polishing rate is low, it is desirable to reduce the roll off before the polishing.
FIG. 2
illustrates an alternate processing sequence described in U.S. Pat. No. 6,294,469 issued Sep. 25, 2001 to Kulkarni et al. The ingot is sliced (step
210
). Then the wafer is subjected to “plasma jet etching” (step
220
) to remove the sub-surface damage caused by the slicing operation. Then a wet etch is performed (“high-gloss etching”, step
230
) to smoothen the wafer. This is followed by “plasma assisted chemical etching” (PACE) at step
240
. PACE involves calculating a point-by-point thickness profile of the wafer, and determining the amount of material to be removed at each point of the wafer surface. The calculated amount of material determines the plasma “dwell time” at each point of the wafer. Then a plasma etch is performed in an apparatus capable to control the plasma in accordance with the calculated dwell times. See also U.S. Pat. No. 5,254,830 issued Oct. 19, 1993 to Zarowin et al.
SUMMARY
This section summarizes some features of the invention. Other features are described in subsequent sections. The invention is defined by the appended claims.
The inventor has observed that the edge roll off can be reduced by a plasma etch if the wafer is held in a particular type of a wafer holder. The plasma etch may or may not be a point-to-point etch, and no point-to-point dwell times are calculated in some embodiments. The wafer holder emits a gas flow (e.g. a vortex of gas) towards the wafer. The gas flow causes a low pressure zone to develop between the holder's body and the wafer. Due to the low pressure, the wafer is held adjacent to the holder's body. The plasma impinges on the wafer surface opposite to the surface facing the body. Some of the gas emitted by the holder wraps around the wafer and dilutes the etchant near the edge. Consequently, the etch proceeds slower near the edge (the wafer is underctched near the edge).
In some embodiments, the wafer rotates around an axis passing through the wafer to make the underetch more uniform along the edge.
Other features and advantages of the invention are described below. The invention is defined by the appended claims.
REFERENCES:
patent: 4668366 (1987-05-01), Zarowin
patent: 5254830 (1993-10-01), Zarowin et al.
patent: 6095582 (2000-08-01), Siniaguine et al.
patent: 6139678 (2000-10-01), Siniaguine
patent: 6168697 (2001-01-01), Siniaguine et al.
patent: 6184060 (2001-02-01), Siniaguine
patent: 6203661 (2001-03-01), Siniaguine et al.
patent: 6287976 (2001-09-01), Siniaguine et al.
patent: 6294469 (2001-09-01), Kulkarni et al.
patent: 6398823 (2002-06-01), Siniaguine et al.
patent: 6402843 (2002-06-01), Siniaguine et al.
patent: 6427991 (2002-08-01), Kao
patent: 6448153 (2002-09-01), Siniaguine et al.
patent: 2002/0187595 (2002-12-01), Walitzki et al.
patent: WO 02/41355 (2002-05-01), None
Wolf, Stanley; Tauber, Richard N. “Silicon Processing for the VLSI ERA, vol. 1: Process Technology” 1986 by Lattice Press, Sunset Beach, California; pp. 23-26.
Elms Richard
MacPherson Kwok & Chen & Heid LLP
Shenker Michael
Smith Brad
Tru-Si Technologies Inc.
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