Wafer with improved sawing loops

Details Wafer with improved sawing loops Wafer with improved sawing loops

2005-07-20

2009-08-18

Tran, Minh-Loan T (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With peripheral feature due to separation of smaller...

C257SE23123, C257SE23194

Reexamination Certificate

active

07576412

ABSTRACT:
In a wafer (1) with chips (2) and elongate separating zones (4) between the chips (2), each chip (2) comprises at least one sawing loop (6), which sawing loop (6) comprises two protecting strips (17, 18) projecting from a planar protecting layer (16) of the chip (2), wherein said protecting strips (17, 18) are widened by means of wider strip portions (26, 27, 28, 29) where they emerge from the planar protecting layer (16), and wherein the protecting strips (17, 18) and the planar protecting layer (16) are provided with weak spots (31, 32, 34) serving as envisaged breakage points.

REFERENCES:
patent: 6465872 (2002-10-01), Tada
patent: 6492247 (2002-12-01), Guthrie et al.
patent: 2002/0016033 (2002-02-01), Bergler et al.
patent: 10 164522 (1998-09-01), None
“PCT International Search Report with mailing date, Feb. 6, 2006, (International Application No. PCT/ IB2005/052428)”.
Patent Abstracts of Japan. Publication No. 10-163522; Application No. 08-319286 titled, “Manufacture of LED Array,” Jun. 19, 1998.

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