Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1996-11-26
2002-10-15
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S762010, C438S018000
Reexamination Certificate
active
06466042
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a probe card used in the probing test of a semiconductor IC chip and a manufacturing method thereof, and more particularly, to a wafer type probe card having micro tips for testing all the IC chips on a wafer simultaneously and a method for manufacturing the same.
BACKGROUND OF THE INVENTION
In recent years, the semiconductor industry has grown rapidly to a very-large-scale-integration (VLSI) technology, which has resulted in the essential of the test process of the integrated circuit (IC) chips formed on the semiconductor wafer for testing the failures of the IC chips.
There are testing methods of the IC chips. One is a wafer probing test for testing chips in a wafer state and the other is a final test for testing chips in a package state.
FIG. 12
shows a general wafer probing test system which can be used for the wafer probing test described above. Referring to
FIG. 12
, a wafer probing test apparatus comprises a wafer chip test system
100
for testing chips in a wafer state; and a test head
101
which is electrically connected to the wafer chip test system
100
. The wafer
103
on which a semiconductor chip
103
A is formed is mounted on a top of a chuck
105
, and the chuck
105
is disposed on a wafer probe station
106
. A probe card
102
A shown in
FIG. 13A
having horizontal needles
108
is set up between the IC chip test head
101
and the wafer
103
. In order to test failures of the semiconductor IC chip
103
A, pads
104
formed on the semiconductor IC chip
103
A are contacted with the horizontal needles
108
mounted on the probe card
102
A. The probe card
102
A having the horizontal needles
108
is electrically connected to the IC chip test head
101
. Accordingly, the wafer chip test system
100
can test the failures of the semiconductor IC chip
103
A with the aid of the horizontal needles
108
mounted on the probe card
102
A which are contacted to the pads
104
.
A conventional probe card
102
A on which the horizontal needles
108
are mounted is shown in more detail in
FIGS. 13A and 13B
.
Generally, each of the horizontal needles
108
has a length ranging from 40 to 50 mm and a diameter range from 200 to 250 &mgr;m. The horizontal needles
108
are made of a conductive metal, preferably tungsten (W), however beryllium-copper (Be—Cu) or paliney-7 (P-7) may also be used as the material for the horizontal needles
108
, considering factors such as hardness, degree of wear and conductivity, etc. Also a metal plated with gold (Au) or copper (CU) may also be used.
After the horizontal needles
108
having bent tips are manufactured from one of the materials described above, a needle module is completed by forming a probe ring
109
made of an epoxy resin for fixing the horizontal needles
108
onto the probe card
102
A. Thereafter, the needle module is fixed onto a ready-made PCB of a probe card. Next, each of the horizontal needles
108
is fixed onto the signal pattern formed on the PCB by soldering. In this case, a microscope is required for working a series of processes necessary for manufacturing the needle module and fixing the horizontal needles
108
onto the PCB. Thus, it is very difficult to control the length of the horizontal needles
108
and to fix the positions thereof, when manufacturing the module needle.
It is also difficult to control and adjust the bending angle of the tips of the horizontal needles
108
when bending the tips. There are other difficulties such as a lengthy process for manufacturing the probe card and high failure rate of the probe card , because it is difficult to maintain a gap between the horizontal needles when mounting the needles onto the signal pattern.
Furthermore, there is another problem that frequency characteristics and impedance characteristics going bad because of the length of the needles
108
. Also, controlling and adjusting the length, width and arrangement of the needles becomes more and more difficult and thus the failure rate increases because the needle module for testing a plurality of semiconductor IC chips is necessarily manufactured by depositing the needle layers in the second, third, and fourth level, etc., due to a spatial limitation in manufacturing the needle module according to the size, arrangement, pitch and position of the pads
104
, which limiteds the number of needles that can be produced. Furthermore, it is difficult to control the tension of each of the needles with a constant value.
Accordingly, due to the problems described in detail above, there is a design limitation when pads are arranged on the semiconductor IC chip, which ultimately leads to a limitation of performance in a multi-chip test.
In FIGS.,
14
A &
14
BB, another conventional probe card is show. the structure of a membrane-type probe card
202
A is basically the same as that of the probe card having horizontal needles. However, in membrane-type probe card
202
A, portions contacting the pads
104
mounted on a semiconductor IC chip are not the horizontal needles, but pointed bumps
212
which can softly contact with the pads
104
. In this case, the tension of the bumps
212
is maintained by a flexible membrane
201
which resultingly leads to a constant contact force being maintained between bumps
212
and pads
104
. Also, as another supplementary units for maintaining tension, a pressure maintaining adjustment tool
204
made of a pivot spring and a pressure-maintaining box cover
203
are formed on the membrane
201
, for smoothly contacting the bumps
212
to the pads
104
and for prohibiting damages of the pads
104
.
Although the membrane-type dot probe card provides substantial remedies for solving many drawbacks of the conventional probe card having horizontal needles, problems remain in the membrane- type dot probe card, because the structure thereof is basically that of a horizontal type. That is, there is, the manufacturing of the membrane-type dot probe card for testing a multiple of semiconductor IC chips has limitations resulting constant tension. Additionally, there is another problem that contact failure in some parts may occur between the bumps
212
and the pads
104
, because it is difficult to control the tension of the membrane
201
. Also, a contact failure between a wafer and a probe card may be occurr because each lengths of the bumps
212
may be very short.
SUMMARY OF THE INVENTION
For solving the above mentioned problems, it is an object of the invention to provide a wafer probe card having silicon micro tips which match with each pad on the wafer, to thereby unify the probing method. Therefore, wafer probing test is available irrelevant to the wafer on which any type of IC chip is mounted and it is possible to test all the IC chips simultaneously. Also, a burn-in test in the wafer state is also possible.
The preceding object should be constructed as merely presenting a few of the more pertinent features and applications of the invention. Many other beneficial results can be obtained by applying the disclosed invention in a different manner or modifying the invention within the scope of the disclosure.
Accordingly, other objects may be had by referring to both the summary of the invention and the embodiment in addition to the scope of the invention defined by the claims considered in conjunction with the accompanying drawings.
For the purpose of summarizing the invention, a wafer probe card having micro tips of the present invention comprises a substrate having a hollow in a portion of a semiconductor wafer, a main layer having a curved micro tip formed on said substrate and a sub layer formed on the main layer.
Also a method how to manufacture a wafer probe card having micro tips of the present invention comprises the steps of forming a n
+
diffusion layer on a silicon wafer, forming a main layer of a n− type epitaxial layer on the n
+
diffusion layer, etching a portion of the main layer by a photolithographic process, transforming the n
+
diffusion layer to a porous silicon by an anode reaction, etc
Karlsen Ernest
Workman & Nydegger & Seeley
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