Wafer structure

Details Wafer structure Wafer structure

2010-12-17

2011-12-13

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

With shielding

C257S797000, C257S660000, C257SE23179

Reexamination Certificate

active

08076758

ABSTRACT:
A wafer structure includes a plurality of dies, an edge portion, a passivation layer, and a UV-blocking metal layer. Each of the dies having an integrated circuit formed thereon, and the circuit includes an upmost metal layer that includes bonding pads. A composite dielectric layer corresponding to dielectric layers of the integrated circuit is disposed on the edge portion, and a cavity is formed in the composite dielectric layer over the edge portion. The passivation layer is located over the whole wafer and covers the upmost metal layer. The UV-blocking metal layer is located on the passivation layer and covers the edge portion and at least a portion of each of the dies. The cavity, the passivation layer, and the UV-blocking metal layer result in an alignment mark.

REFERENCES:
patent: 5911108 (1999-06-01), Yen
patent: 6765254 (2004-07-01), Hui et al.
patent: 6774432 (2004-08-01), Ngo et al.
patent: 7038777 (2006-05-01), Kim et al.

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