Wafer street buffer layer

Details Wafer street buffer layer Wafer street buffer layer

2008-03-11

2008-03-11

Coleman, W. David (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With peripheral feature due to separation of smaller...

C438S113000, C257SE23123

Reexamination Certificate

active

07342296

ABSTRACT:
The present invention provides a separating process of a semiconductor device package of wafer level package. The method comprises a step of etching a substrate to form recesses. Then a buffer layer is formed on the first surface of the substrate, wherein the buffer layer is filled with the corresponding recesses to form infillings on adjacent the semiconductor device package. Dicing the wafer into individual package along substantial center of said infillings, the step may avoid the roughness on the edge of each die and also decrease the cost of the separating process.

REFERENCES:
patent: 6207477 (2001-03-01), Motooka et al.
patent: 7144760 (2006-12-01), Hanaoka
patent: 2003/0100143 (2003-05-01), Mulligan et al.
patent: 2004/0121563 (2004-06-01), Farnworth et al.

Affiliated with

Also associated with

Rating

Wafer street buffer layer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer street buffer layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer street buffer layer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2806733