Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
2002-01-02
2004-05-04
Picard, Leo (Department: 2125)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
Reexamination Certificate
active
06731999
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates generally to optimization of scheduling and release of foundry fab wafer orders and, more particularly, to a lot release control algorithm in a foundry fab producing multiple products that have different due dates and different process flows.
2. Description of Related Art
In a typical foundry making wafers there are many constraints that affect the efficiency of the process. For optimization of the entire process there must be an attempt to maximize the output of the wafers and minimize the entire cycle from start to finish. There is no systematic optimized order release model that provides this scheduling. With the many variables present in running a wafer fab line, conflicts may result in idle time for the tools and wait time for the product. Even worse, promised delivery dates to customers can be missed when the wafer fab becomes too busy due to conflicts and delays with other processing.
On-time delivery of wafer is also impacted by bottlenecks caused by tool problems. Once tool problems present themselves, all schedules using the malfunctioning tools are delayed. This can cause a ripple effect that has a major impact on the current customer's wafers and on subsequent orders. Without a good method to factor in these impacts, it becomes difficult to give the customers accurate new completion dates. With optimized order release capability, schedules can more successfully be met with the result of happier and retained customers.
Several methods or systems related to wafer process control are available. In U.S. Pat. No. 4,887,218 (Natarajan) a conceptual decision analysis tool for production release planning is described. In U.S. Pat. No. 5,369,570 (Parad) a method for continuous real-time management of heterogeneous interdependent resources is described. In U.S. Pat. No. 5,796,614 (Yamada) a level-by-level explosion method for material requirements planning is provided. In U.S. Pat. No. 5,594,639 (Atsumi) an order process control model is described. In U.S. Pat. No. 6,119,102 (Rush et al.) a Manufacturing Requirements Planning (MRP) system is provided. Finally, in U.S. Pat. No. 5,093,794 (Howie et al.) a job scheduling system for jobs without special purpose coding is provided.
An optimized order release algorithm could save significant time and money in a number of situations and cut down on missed schedules that could result in a loss of customers.
SUMMARY OF THE INVENTION
This invention provides a start order release method to achieve maximum output with a minimum of cycle time, thus saving processing time and money due to the increased efficiencies from the method. The first overall objective is to provide a control model that with a planned step-by-step process optimizes release of work lots in a manufacturing line.
A second, more specific, objective is to provide a set of control algorithms to determine the most optimum control model for production of lots, taking into consideration the start date of processing, the committed due date, theoretical process time, and customers' needs.
Another specific objective is to provide lower and upper bound constraints to control the processing using linear programming techniques on which the final development of the Start To Build (STB) plan is based.
These objectives are achieved by using a specified lot release algorithm. The algorithm takes into account multiple products that have different due dates plus different process flows. Using the algorithms with linear program techniques, the method of this invention produces more accurate start schedules and high resource utilization while minimizing the number of late orders. This method has been found useful for foundry wafer fab systems to maximize output in wafer production and minimize cycle time in real production environments.
REFERENCES:
patent: 4887218 (1989-12-01), Natarajan
patent: 4896269 (1990-01-01), Tong
patent: 5093794 (1992-03-01), Howie et al.
patent: 5369570 (1994-11-01), Parad
patent: 5594639 (1997-01-01), Atsumi
patent: 5796614 (1998-08-01), Yamada
patent: 5818716 (1998-10-01), Chin et al.
patent: 6119102 (2000-09-01), Rush et al.
patent: 6272389 (2001-08-01), Dietrich
Chu James
Yang Terry
Ackerman Stephen B.
Jarrett R
Picard Leo
Saile George O.
Taiwan Semiconductor Manufacturing Company
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