Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-08-15
2004-12-07
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
With measuring or testing
C700S121000, C702S081000
Reexamination Certificate
active
06828163
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method and an apparatus for evaluating a configuration of a wafer represented by a silicon wafer. The present invention also relates to a semiconductor device fabricating method, especially to a wafer enabling improvement in a yield in a device fabricating process using an exposure system, and a sorting method for the same.
BACKGROUND ART
Conventionally, a method for manufacturing a silicon wafer used as a semiconductor substrate material generally comprises a crystal growth process for producing a single crystal ingot by a Czochralski (CZ) method, a floating zone melting (FZ) method or the like, and a wafer manufacturing process for manufacturing a wafer by slicing this single crystal ingot and processing at least one main surface thereof into a mirror-like surface. To describe the process more detailedly, the wafer manufacturing process comprises, a slicing step of slicing the single crystal ingot to obtain a thin and disk-shaped wafer; a chamfering step of chamfering a peripheral edge portion of the wafer obtained through the slicing step to prevent cracking and chipping of the wafer; a lapping step of flattening this wafer; an etching step of removing machining deformation remaining in the so chamfered and lapped wafer; a polishing step of making a mirror surface of the wafer; and a cleaning step of cleaning the polished wafer to remove a polishing agent or dust particles deposited thereon. The main steps of the wafer manufacturing process are only listed above, and sometimes other steps such as a heat treatment step may be added, or the step sequence may be changed.
Recently, an integration level in a semiconductor device has been becoming increasingly higher because of the remarkable progress in the semiconductor device technology, and with this progress, a demand for quality of a silicon wafer or the like has also been becoming more severe. A semiconductor device is fabricated by using a mirror-polished wafer which has been subjected to the single crystal producing process and the wafer manufacturing process. In the device fabricating process, a step of forming a resist pattern is repeatedly performed 20 to 30 times. Recently, a higher integration level and higher performance in a semiconductor integrated circuit has been advanced remarkably, and in company with this tendency, more miniaturization of circuit patterns is required. Taking a DRAM (dynamic random access memory) as an example, in a 64M bit DRAM that is now in quantity production, a resist pattern of 0.25 &mgr;m to 0.20 &mgr;m is drawn. In a photolithography step, a KrF excimer laser (wavelength=248 nm) of ultraviolet radiation is used as a light source most frequently. Further, with miniaturization of patterns, also improvement in dimension accuracy and overlay accuracy is required. With this progress, also a demand for quality of a silicon wafer or the like used as a base for a device has been becoming more severe.
That is, this is because a higher integration level of a semiconductor device has brought out miniaturization of a device size, and for instance, slight undulation or the like on a silicon wafer may lead to errors in a device pattern during the photolithography step or other steps. In addition, in order to effectively use a wafer, there is required a wafer which has excellent flatness up to the utmost outer peripheral portion (the very limit of the chamfered portion) of its main surface.
As one of the important characteristics required to the silicon wafer as described above, there is a problem of shape quality thereof. The wafer shape quality includes various parameters such as a diameter, a thickness, parallelism, flatness, irregularities with a relatively longer cycle named sori, bow, warp or the like, irregularities with a cycle of several mm named undulation and surface roughness; recently, it is frequently evaluated by quality named global flatness or site flatness based on a back side reference or a front side reference as an index of flatness.
Especially, as the index of flatness, the global flatness based on the back side reference is named GBIR (Global Back Ideal Range); this is usually defined, assuming that a reference plane is prepared within a wafer surface, as a width between the maximum positional displacement and the minimum positional displacement against the reference plane, and corresponds to TTV (Total Thickness Variation) which is a conventional specification.
Also, the site flatness based on the back side reference is named SBIR (Site Back Ideal Range), and corresponds to LTV which was quite frequently used in the past. When a back surface of a wafer is used as a reference plane and further at each site a plane including a center of the site is employed as a focal plane, the SBIR is a sum of absolute values of the respective maximum displacements in the plus side and minus side from the focal plane in the site, which is evaluated for each site. Usually, in case of an 8-inch wafer or the like, this value is evaluated in an area having a site of the order of 20 mm×20 mm. The size of this site varies depending upon a diameter or specifications of a wafer.
Moreover, the site flatness based on the front side reference is named SFQR (Site Front Least Squares Range); this is a sum of absolute values of the respective maximum displacements in the plus side and minus side from the reference plane which is a flat plane in a site obtained by calculating data with the method of least squares, which is evaluated for each site within a prescribed site.
Further, quality named nanotopography has been taken seriously. The nanotopography (also named nanotopology) means irregularities with a wavelength of the order of from 0.1 mm to 20 mm and an amplitude of the order of from several nm to 100 nm; the evaluation method therefor is performed by evaluating a difference of altitude of irregularities (a PV value; peak to valley) on a wafer surface in a range of a square block having a side of the order of from 0.1 mm to 10 mm, or of a circular block having a diameter of the order of from 0.1 mm to 10 mm (this range is named WINDOW SIZE or the like). This PV value is also named Nanotopological Height or the like. As the nanotopography, it is desired that the maximum value of the irregularities present within the evaluated wafer surface is small. Usually, this value of a wafer is evaluated by the maximum value among PV values obtained through evaluation of a plurality of blocks with a square having a side of 10 mm, and when this value is 60 nm or less, it is determined that the evaluated wafer is a good chip.
Up to a design rule of 0.18 &mgr;m in the device fabricating process, it was enough to manufacture a wafer that meets standard requirements under evaluation with the above-mentioned index, but as recently the design rule has been becoming increasingly severe with a specification of 0.15 &mgr;m or even 0.13 &mgr;m, when a wafer that meets the above standard requirements was used for fabricating an actual device, there sometimes took place decrease of its yield. Accordingly, there are required a wafer manufacturing method and a wafer evaluating method in which a wafer is prescribed by factors other than the above-mentioned indexes and specifications of severe design rules are carried out without any problem.
Especially, with the above-mentioned GBIR, SBIR, SFQR, or the like, although flatness at the middle side portion of a wafer can be precisely evaluated, flatness at a peripheral portion thereof, especially a portion in the vicinity of a boundary between a chamfered portion and a main surface of a wafer is sometimes not evaluated precisely.
For instance, in the device fabricating process, many processing machines such as an exposure system and other machines are used, and compatibility between a wafer holding chuck used in each machine and a configuration of a wafer to be processed has been becoming an issue. Matching between undulation and a peripheral shape of the chuck and those of the wafer is important, but it is impossible
Kobayashi Makoto
Maejima Shinroku
Matsukawa Kazuhito
Yamamoto Hidekazu
Pert Evan
Rader & Fishman & Grauer, PLLC
Shin-Etsu Handotai & Co., Ltd.
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