Wafer scale semiconductor structure

Details Wafer scale semiconductor structure Wafer scale semiconductor structure

2007-05-08

2007-05-08

Louie, Wai-Sing (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S774000

Reexamination Certificate

active

09045507

ABSTRACT:
A chip scale package structure formed by adhering a glass sheet having a pattern of holes matching a pattern of bond pads on a semiconductor wafer so that the pattern of holes on the glass sheet are over the pattern of bond pads on the semiconductor wafer. Metallized pads are formed on the glass sheet adjacent to each hole and in one embodiment a conductive trace is formed from each metallized pad on the glass sheet to the bond pad on the semiconductor wafer under the adjacent hole. In a second embodiment, a pad is formed on the glass sheet adjacent to each hole and the pad extends down the sides of the adjacent hole. The hole is filled with a metal plug that electrically connects the pad on the glass sheet to the bond pad on the semiconductor wafer. In each embodiment a solder ball is formed on each pad on the glass sheet.

REFERENCES:
patent: 5258648 (1993-11-01), Lin
patent: 5468681 (1995-11-01), Pasch
patent: 5705858 (1998-01-01), Tsukamoto
patent: 5814894 (1998-09-01), Igarashi et al.
patent: 5844304 (1998-12-01), Kata et al.
patent: 5973337 (1999-10-01), Knapp et al.
patent: 6300235 (2001-10-01), Feldner et al.
patent: 6303977 (2001-10-01), Schroen et al.

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