Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1999-07-15
2001-12-25
Cuneo, Kamand (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C361S794000, C361S795000, C438S113000
Reexamination Certificate
active
06333469
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wafer-scale package structure for rearranging and packaging electrode pads in a lump and in the form of a wafer, and a circuit board used in such a wafer-scale package structure.
The present application is based on Japanese Patent Application No. Hei. 10-202227 which is incorporated herein by reference.
2. Description of the Related Art
With miniaturization and realization of high-performance in electronic equipments in recent years, semiconductor devices constituting the electronic equipments and multilayer printed-wiring boards mounted with the semiconductor devices have been required to be small and thin and to have high performance and high reliability. Under such conditions, packages have been miniaturized, and semiconductor devices which are substantially as large as chips and called chip-size packages (CSPs) have been developed. Various methods have been proposed for the chip-size packages, but usually, chips subjected to dicing are packaged individually one by one. For example, often used is a method in which fine electrode pads on each chip are rearranged in the form of a grid and sealed with resin or the like.
However, since chips cut out of a wafer are packaged individually one by one, the above-mentioned method has problems that the productivity deteriorates, the cost increases, and so on.
SUMMARY OF THE INVENTION
Taking the foregoing situation into consideration, it is an object of the present invention to provide a wafer-scale package structure and a circuit board used in the wafer-scale package structure which are high in productivity and low in cost.
In order to achieve the object, a first gist of the present invention is in a wafer-scale package structure arranged so that a circuit board for rearranging electrode pads of a wafer is laminated on the wafer integrally, wherein the circuit board can be divided into individual chip-size packages (CSPS) and includes an insulating layer made from polyimide resin as a main ingredient, and connection between the wafer and the circuit board is performed by solder, while the circuit board is laminated on the wafer with an adhesive. Further a second gist of the present invention is in a circuit board for use in the above-mentioned wafer scale structure so as to rearrange electrode pads of the wafer, wherein solder bumps are formed in electrode portions of the circuit board corresponding to the electrode pads of the wafer to make connections between the electrode portions and the electrode pads.
That is, a wafer-scale package structure according to the present invention is designed so that a circuit board for rearranging electrode pads of a wafer is laminated on this wafer in a lump. The circuit board is a circuit board which can be divided into individual chip-size packages (CSPS) and which is constituted by an insulating layer containing polyimide resin as a main ingredient. The connection between the wafer and the circuit board is performed by solder, while the circuit board is stuck on the wafer by an adhesive. In such a manner, in the wafer-scale package structure according to the present invention, chips subjected to dicing are not packaged individually one by one, but the chips are subject to rearrangement of electrode pads and at the same time they are packaged in a lump in the form of a wafer, and thereafter they are cut into individual CSPs. Accordingly, the productivity becomes high, and the cost can be reduced. In addition, in the circuit board according to the present invention, solder bumps are formed respectively in electrode portions of the circuit board. The connection between the wafer and the circuit board is performed by means of these solder bumps, so that all the connections can be performed in a lump. Accordingly, the electric reliability is also extremely high. The solder also includes a solder free from lead like Bi—Sn, Ag—Sn or the like.
In the wafer-scale package structure according to the present invention, the above-mentioned insulating layer includes metal foil with low thermal expansivity. In this case, the thermal expansivity of the circuit board can be reduced by this metal foil and made close to the thermal expansivity of the wafer. Accordingly, a warp of the wafer is reduced.
In the circuit board according to the present invention, solder bumps are formed in electrode portions of the circuit board corresponding to electric connection portions of a mother board to make electric connections between the circuit board and the mother board. In this case, it is not necessary to mount solder balls in addition after the circuit board is stuck on the wafer.
In the circuit board according to the present invention, the melting point of the solder provided in the electrode portions of the circuit board corresponding to the electrode pads is made higher than the melting point of the solder provided in the electrode portions of the circuit board corresponding to the electric connection portions of the mother board. In this case, there is no fear that the solder in the wafer-scale package structure (solder for connection with the electrode pads) melts at a temperature at which the circuit board is mounted on the mother board. Accordingly, there is no fear that the reliability of the connection is reduced by the mounting of the circuit board onto the mother board.
Features and advantages of the invention will be evident from the following detailed description of the preferred embodiments described in conjunction with attached drawings.
REFERENCES:
patent: 5848467 (1998-12-01), Khandros
patent: 6096574 (2000-08-01), Smith
Pan-Pacific Electronics Symposium published material Feb. 13, 1998.
Inoue Yasushi
Nagasawa Megumu
Nakamura Kei
Okeyui Takuji
Sugimoto Masakazu
Cuneo Kamand
Nitto Denko Corporation
Sughrue & Mion, PLLC
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