Wafer scale package and method of assembly

Details Wafer scale package and method of assembly Wafer scale package and method of assembly

2005-09-06

2005-09-06

Nguyen, Ha Tran (Department: 2812)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Having enclosed cavity

C438S113000, C438S458000

Reexamination Certificate

active

06939784

ABSTRACT:
A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.

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