Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With large area flexible electrodes in press contact with...
Reexamination Certificate
2003-03-26
2004-11-02
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With large area flexible electrodes in press contact with...
C257S689000, C257S692000, C257S698000, C257S727000
Reexamination Certificate
active
06812558
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
The invention in general relates to the packaging of electronic circuits, and particularly to those including MEMS devices.
2. Description of related art
A variety of MEMS (microelectromechanical systems) switches are in use, or proposed for use, in biomedical systems, in radar and communication systems, as well as other high frequency circuits for controlling RF signals. These MEMS switches are popular insofar as they can have a relatively high off impedance, with a low off capacitance, and a relatively low on impedance, with a high on capacitance, leading to desirable high cutoff frequencies and wide bandwidth operation. Additionally, the MEMS switches have a small footprint, can operate at high RF voltages and are compatible with conventional integrated circuit fabrication techniques.
For example, electronic circuits including MEMS switches are generally fabricated and tested on a large scale wafer which is subsequently cut up (diced) into individual circuits. These individual circuits are then packaged and placed into other systems.
Many of these MEMS switches generally have electrostatic elements, such as opposed electrodes, which are attracted to one another upon application of a pull down control voltage. At least one of these pull down electrodes is on the wafer and an opposing electrode is defined on the underside of a moveable bridge, or cantilever, above the wafer. Upon application of the pull down control voltage, the bridge, or cantilever is deflected down and the electrical impedance is severely reduced (either by capacitive coupling or by direct ohmic contact), between first and second spaced apart RF conductors on the wafer thus allowing a signal to propagate between the first and second RF conductors.
In view of the fact that these MEMS switches have electrically movable components, such as the bridge, it is imperative that movement of these components be completely unimpeded. However, after the fabrication process, in a wafer processing clean room, it is possible that unwanted debris blocks the normal movement of the bridge. This debris can occur particularly as a result of the dicing and packaging steps or in an application environment.
The MEMS device is not only sensitive to air borne particulates but also to moisture to which the MEMS device may be subject after it leaves the wafer processing clean room.
The present invention provides for a wafer scale packaging resulting in a hermetically sealed unit which eliminates the problems of conventional fabrication. In addition, the present invention is conducive to assembly under desired controlled ambient conditions.
SUMMARY OF THE INVENTION
A wafer scale package for electronic circuits is described and includes a base wafer having a plurality of locations each accommodating an electronic circuit, each circuit including at least one electronic device and associated signal lines. A cover wafer is provided having a corresponding like plurality of locations each including at least one cavity of sufficient size to accommodate the electronic device. Each location of the cover wafer includes a plurality of electrically conducting vias for establishing electrical continuity with the signal lines, at the bottom of the vias. A multilayer metallic seal surrounds each location to provide a peripheral hermetic seal and a multilayer metallic seal surrounds each bottom of the vias to provide a via hermetic seal. The peripheral hermetic seal is of sufficient width to enable dicing along the peripheral hermetic seal to form individual die packages, each containing a hermetically sealed electronic circuit.
Further scope of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood, however, that the detailed description and specific example, while disclosing the preferred embodiment of the invention, is provided by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art, from the detailed description.
REFERENCES:
patent: 5998875 (1999-12-01), Bodo et al.
patent: 6236109 (2001-05-01), Hsuan et al.
patent: 6281569 (2001-08-01), Sugiyama
patent: 6472305 (2002-10-01), Ozaki et al.
Chen Li-Shu
Fudem Howard
Moloney Thomas J.
Smith Philip C.
LandOfFree
Wafer scale package and method of assembly does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Wafer scale package and method of assembly, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer scale package and method of assembly will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3342466