Wafer scale integration system

Details Wafer scale integration system Wafer scale integration system

1975-07-28

1977-02-08

Trafton, David L.

Communications: electrical

Digital comparator systems

307303, 357 45, 340173AM, 340173SP, G11C 1700

Patent

active

040074528

ABSTRACT:
A system and method for interconnecting a plurality of separate memories (on other circuits) on a wafer so as to electrically exclude defective memories and include operative memories. A single discretionary connection is associated with each of the separate memories and such connection is made (or broken) after a memory is tested. In addition to a bidirectional memory bus used for input/output data and addresses, the wafer includes a separate identity bus used to define the memory organization. The identity bus is interconnected by a plurality of incrementers, one associated with each memory. The signal on the identity bus is incremented by useable memories and such signal is compared to an address on the bidirectional memory bus to select memories in an organized manner.

REFERENCES:
patent: 3475733 (1969-10-01), Gaines et al.
patent: 3644904 (1972-02-01), Baker
patent: 3644906 (1972-02-01), Weinberger
patent: 3691538 (1972-09-01), Haney et al.
patent: 3755791 (1973-08-01), Arzubi
patent: 3765001 (1973-10-01), Beausoleil
patent: 3803562 (1974-04-01), Hunter
patent: 3810301 (1974-05-01), Cook
patent: 3881175 (1975-04-01), Wanlass

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