Wafer scale integration of electroplated 3D structures using...

Details Wafer scale integration of electroplated 3D structures using... Wafer scale integration of electroplated 3D structures using...

2007-01-30

2007-01-30

Smith, Zandra V. (Department: 2822)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

C438S106000, C438S124000

Reexamination Certificate

active

11012597

ABSTRACT:
Wafer scale fabrication of three dimentional substantially enclosed structures on a MEMS/IC die use a combination of electrodeposition of structural and sacrificial layers and flip-chip alignment and bonding technology. A first wafer contains a die with MEMS and/or IC structures. On this MEMS/IC processed die, a first three dimensional structural component is formed using standard lithographic processes and electrodeposition of a structural layer. A second sacrificial wafer is separately processed using similar lithographic and electrodeposition processes to form a corresponding second three dimensional structural component. The wafers are placed in a flip-chip bonder and aligned. Once aligned, the structural components are bonded together. The bonded wafers are then removed from the bonder and the second sacrificial wafer substrate removed. The resultant die includes a three dimensional structural component with a substantially enclosed cavity as well as MEMS and IC elements.

REFERENCES:
patent: 6475369 (2002-11-01), Cohen
patent: 6872319 (2005-03-01), Tsai
patent: 2003/0127336 (2003-07-01), Cohen et al.
patent: 2003/0183008 (2003-10-01), Bang et al.
patent: 2003/0221968 (2003-12-01), Cohen et al.
patent: 2003/0222738 (2003-12-01), Brown et al.
patent: 2003/0234179 (2003-12-01), Bang
patent: 2004/0004001 (2004-01-01), Cohen et al.
patent: 2004/0004002 (2004-01-01), Thompson et al.
patent: 2004/0007468 (2004-01-01), Cohen et al.
patent: 2004/0007469 (2004-01-01), Cohen et al.
patent: 2004/0007470 (2004-01-01), Smalley
patent: 2004/0020782 (2004-02-01), Cohen et al.
patent: 2004/0140862 (2004-07-01), Brown et al.

Affiliated with

Also associated with

Rating

Wafer scale integration of electroplated 3D structures using... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer scale integration of electroplated 3D structures using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer scale integration of electroplated 3D structures using... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3722994