Wafer scale integration

Details Wafer scale integration Wafer scale integration

1985-12-16

1989-09-12

Wojciechowicz, E.

Electricity: electrothermally or thermally actuated switches

Electrothermally actuated switches

With bimetallic elements

357 49, 357 55, 357 67, 357 68, 357 71, 357 81, H01L 2704

Patent

active

048665010

ABSTRACT:
A circuit package comprises at least one IC chip bonded directly in a hole provided in a wafer such that the surface of the chip and the surface of the wafer are in the same plane thereby accommodating TAB bonding of the chip to bonding pads provided on the wafer. The structure can include multilayer circuitry on the wafer.

REFERENCES:
patent: 4352120 (1982-09-01), Kurihara et al.
patent: 4468887 (1984-09-01), Christian et al.
patent: 4484215 (1984-11-01), Pappas
patent: 4530001 (1985-07-01), Mori et al.
"The Basics of Tape Automated Bonding" by Phil W. Rima, Hybrid Circuit Technology, Nov. 1984, pp. 15-21.
Electronics, "Japan's Packaging Goes World Class", C. L. Cohen, 11/85, 26-31.
35th Electronic Components Conf., "Packaging Technology for the NEC SX Supercomputer", NEC Corporation, T. Watari et al., IEEE 1985, 192-198.

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