Wafer scale integrated circuit memories

Details Wafer scale integrated circuit memories Wafer scale integrated circuit memories

1981-10-28

1985-07-09

Popek, Joseph A.

Static information storage and retrieval

Addressing

364900, G11C 1300

Patent

active

045286477

ABSTRACT:
A data storage cell is provided for use when concatenated with similar cells in a wafer-scale integrated circuit as part of a serial memory chain. Data is stored in or retrieved from a shift register. A data switch is operable, dependently upon a selectable match criterion being met between the successive contents of a key word register and selectable sections of the data stored in register, the particular sections so selected being controlled by the contents of a control register. The access control is such that records are selectively stored in, or retrieved from, a particular cell dependent upon the content of the records themselves thus removing the necessity for keeping track of the position of records in the serial memory chain. The switch is selectably operable to provide a copy of the circulating contents of the data storage register as the signal on a data output line of the cell, so providing a means for non-destructive readout from the cell. The switch also provides the means of moving many data records along the serial memory chain simultaneously so that any desired ordering of the data records can be preserved during the insertion or deletion of individual data records.

REFERENCES:
patent: 3475733 (1969-10-01), Gaines et al.
patent: 4037205 (1977-07-01), Edelberg et al.
patent: 4255672 (1981-03-01), Ohno et al.
R. C. Aubusson et al., "Wafer-Scale Intergration, A Fault-Tolerant Procedure", I.E.E.E. Journal of Solid State Circuits, vol. SC-13, No. 3, Jun. 1978, pp. 339-344.
F. B. Manning, "An Approach to Highly-Integrated, Computer-Maintained Cellular Arrays", I.E.E.E. Transactions on Computers, vol. C-26, No. 6, Jun. 1977, pp. 536-552.
C. A. Finnila et al., "Associative Linear Array Processor", I.E.E.E. Transactions on Computers, vol. C-26, No. 2, Feb. 1977, pp. 112-125.
Y. Egawa et al., "A 1Mb Full Wafer MOS RAM", I.E.E.E. International Solid State Circuits Conference; Digest of Technical Papers, Feb. 1979, pp. 18-19.

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