Wafer scale integrated circuit

Details Wafer scale integrated circuit Wafer scale integrated circuit

1982-05-13

1984-08-21

Kucia, R. R.

Electricity: electrical systems and devices

Miscellaneous

174 685, 357 45, 361406, 361409, H05K 0118

Patent

active

044674007

ABSTRACT:
Disclosed is a substrate for an array of integrated circuit dice 10' disposed in a regular array on the monolithic wafer substrate 1. Also disposed on the wafer substrate 1 is a network 11' interconnecting various circuits 10', with other integrated circuits, disposed in the array formed on the wafer for data transfer therebetween. Terminals 12' exist in the network 11' for connection of the connections of the network with the various integrated circuits 10'. The networks are connected to a contact pad by one or more connection pads 13', for power and for data entry, and there is provided an auxiliary lead and contact pad for each network for testing each network for operability, also disclosed in the testing method.

REFERENCES:
patent: 3312871 (1967-04-01), Seki et al.
patent: 3445823 (1969-05-01), Petersen
patent: 3558992 (1971-01-01), Huener et al.
patent: 3726002 (1973-04-01), Greenstein et al.
patent: 3777221 (1973-12-01), Tatsuko
patent: 3803483 (1974-04-01), McMahon
patent: 3981070 (1976-09-01), Buelow et al.
patent: 4234888 (1980-11-01), Calhoun
patent: 4295182 (1981-10-01), Aubusson et al.
patent: 4364044 (1982-12-01), Kusano

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