Wafer probe card

Details Wafer probe card Wafer probe card

1999-03-24

2001-07-24

Karlsen, Ernest (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S765010, C324S754090

Reexamination Certificate

active

06265888

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor testing devices and to testing and/or burn-in methods for semiconductor devices, and particularly to the testing of high density integrated circuits such as DRAMs, SRAMs and embedded devices including “system on a chip” and graphic accelerators with embedded DRAM.
2. Description of the Related Art Integrated circuit devices, including DRAM and SRAM memory devices, are typically tested several times at the wafer level and again after dicing and packaging to ensure device quality and reliability. In a conventional testing process, individual devices on the wafer are tested to distinguish good devices from defective ones. The defects found at this stage of testing typically originated during device fabrication. If redundant circuits are present on the devices, a test/sort process is performed to detect reparable devices, which are typically laser repaired to activate the redundant circuitry. The good devices are sorted from the irreparable defective devices. A wafer separation unit, such as a scribe and break mechanism, separates the wafer into individual devices or die, and the good devices are individually packaged. After packaging, a pre-burn-in test (or open/short test) is typically performed to screen out packaging assembly defects, for example shorts or the existence of leakage current that will further degrade during burn-in. Burn-in is then performed in the form of a reliability stress test designed to accelerate failure mechanisms by operating at elevated temperatures. Following burn-in, a post burn-in test is performed to screen out the burn-in stress test defects. Those devices lost during burn-in are devices that likely would fail before the end of their specified life during normal operation. Defects are identified in these parts because the failure modes of the parts are accelerated by the burn-in process. The devices are then unloaded from the burn-in apparatus and a speed test at high temperature is performed. The packaged devices are then marked, and final tests are carried out to ensure that they will operate reliably at room temperature. Consequently, four or five different tests and anywhere from four to seventy-six hours of burn-in are required to ensure the quality and reliability of any given device.
High-density memory integrated circuits, e.g. 64 megabit or larger memory chips, require even longer test times than prior generation memories, since more time is needed to test these larger memory chips due to the longer execution test pattern. In addition, to achieve an acceptable level of yield from high density memories, extra die repair tests and processes are typically needed. At the end of these test and repair cycles, often 60-80% of the finally yielded good parts have undergone repairs. This more significant level of testing required by higher density memories can be costly and time-consuming. Conventional wafer probe technology may only test a single die at a time, or at most, up to 32 die simultaneously, and simultaneous testing of a greater number of die is constrained, in part, by the physical limitation of probe tip design.
Conventional wafer probing systems have relatively long probe tips which cause impedance mismatch problems when tests are carried out on the high density memory units. As the density of a device increases, high speed testing becomes necessary, and the tester must have good high frequency characteristics. Accordingly, probe lengths should be reduced as much as possible to allow testing at high speed or at high temperatures using a high frequency test signal. Due to the above limitations, post burn-in testing of high speed devices is typically performed after packaging. Such discrete component testing requires a large quantity of expensive burn-in systems, burn-in boards with expensive sockets that can accept packaged units, and additional labor associated with the loading and unloading of individual devices to and from the burn-in board. Further, these conventional processes typically scrap an additional one to three percent of the devices after post burn-in that would otherwise have been repairable through activation of redundant circuitry had they not been packaged before the burn-in test. The total cost per yielded packaged device is therefore unnecessarily increased by the equipment cost of the discrete component testing, the loss of devices that would be repairable had their defects been detected at the wafer level and the requirement of additional test cycles for the packaged parts. Accordingly, there is a need for a wafer level defect and reliability testing apparatus that can also perform many of the tests that currently take place after packaging. For example, it would be advantageous to perform the burn-in and high-temperature/high speed testing on all devices simultaneously while they are still in wafer form.
SUMMARY OF THE PREFERRED EMBODIMENTS
The present invention relates to a probe card with a short probe length to enable high temperature, high speed testing of high density devices while reducing the impedance mismatching problems typically associated with such testing. The invention may also relate to a probing and heating apparatus that uses the probe card to enable substrate level testing at elevated temperatures and methods for using the apparatus to test and burn-in devices at the substrate, e.g. wafer, level.
A probe card for electrically interfacing a plurality of devices on a substrate to be tested to a testing unit includes a plurality of probe tips disposed on a surface of the probe card facing the substrate and arranged in a manner corresponding to a plurality of contact pads on the devices of the substrate. The probe card also includes a plurality of signal contacts for conducting signals to and from the testing unit, each signal contact electrically connected to a probe tip. Use of preferred embodiments of the present invention may provide reduced impedance mismatch during high speed testing of high density semiconductor devices.
The probe card described is included in a substrate probing and heating apparatus for testing the electrical characteristics of a plurality devices on a substrate at a plurality of temperatures. The probing and heating apparatus also includes a support unit to align and hold the substrate and the probe card to one another. The support unit includes two support members that may be disengagably coupled to one another. A substrate is removably mounted on a planar surface of the first support member, the substrate having device contact pads facing away from the planar surface. The first support member also includes a heater. The probe card is removably mounted on a second support member. The apparatus also includes a means for disengagably coupling the first member and the second member to one another in a fixed position with the substrate and probe card therebetween to achieve electrical contact between each probe tip of the probe card and the corresponding contact pad of the substrate. Use of preferred embodiments of the present invention may allow testing of high density devices at high speeds in substrate form thereby eliminating a number of steps of the conventional process required when the substrate is separated into individual packaged units before performing certain tests such as burn-in.
A method for handling and testing a plurality of devices on a substrate at a plurality of temperatures includes the steps of providing a substrate having a plurality of devices to be tested through a plurality of contact pads, providing a probing and heating apparatus as described above, a defect testing system and a heater driver/control unit. The substrate is mounted on the first member of the support unit and the two support members are coupled to one another. The substrate is then heated to a pre-determined temperature and the electrical characteristics of the devices are tested with the tester while the devices are maintained at the pre-determined temperature. In other em

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