Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed
Reissue Patent
1992-03-16
2003-03-11
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Optical characteristic sensed
C438S693000, C156S345420, C451S211000
Reissue Patent
active
RE038029
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates to a method of planarizing workpieces utilizing an abrasive slurry in conjunction with a polishing pad.
2. Background Art
In the art of forming metallic interconnection layers on processed semiconductor substrates, it is known that various processing difficulties are presented if the primary passivation layer has an irregular topography. Such difficulties include unacceptable variations i metal layer thickness, which result in the possibility of undesired metal opens/shorts.
At first, this problem was dealt with by using a passivation material (such as phosphosilicate glass (PSG) or boro-phosphosilicate glass (BPSG)) that could be melted (or reflowed) to smooth out the upper surface. While this solution was perfectly acceptable for the device densities of the day, recent advances in integration have forced workers in the art to consider other alternatives. One such alternative is the socalled “planarizing etch-back” procedure, in which a layer of conventional photosensitive polymer (or “photoresist”) is spin-applied on top of the passivation layer. The photoresist presents a planar upper surface. Then using an etch technique that is non-selective between the photoresist and the passivation layer, the layers are simultaneously etched such that the planar upper surface of the photoresist is transferred to the underlaying passivation layer. Such etch processes include sputter etches and reactive ion etches (RIE) in CF
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plasmas. For example, see U.S. Pat. No. 4,710,264 (issued 12/1/87 to Waschler et al and assigned to Telefonken GmbH). This alternative has not been widely accepted in the art because it is very difficult to accurately determine etch endpoint.
Another alternative presently under consideration is the so-called “chem-mech polish” (CMP) process. In this process, passivated substrates are rotated against a polishing pad in the presence of an abrasive slurry. Typically the slurry is pH-controlled such that the etch rate of the passivation layer can be controlled. In U.S. Patent Application Ser. No. 791,860, entitled “Chem-Mech Polishing Method for Producing Co-Planar Metal/Insulator Films On a Substrate,” filed Oct. 28, 1985, by Beyer et al and assigned to the assignee of the present invention, different slurry chemistries are used to optimize insulator-to-metal (or visa-versa) etch rate ratios to achieve a planar surface. For example, using an abrasive pad at a pressure of 2-8 PSI, and a slurry of 0.06 micron alumina particles in deionized water, a 1:1 etch rate ratio of metal:insulator was achieved. The metal etch rate increased (and the oxide etch rate decreased) as different acids are used to lower the pH to 2.2. Alternatively, by increasing the pH to 11-11.5, the insulator removal rate increased relative to metal when using silica particulates at a concentration of 1-10 weight. In U.S. Patent Application Ser. No. 085,836 entitled “Via Filling and Planarizing Technique,” filed Aug. 17, 1987, by Cote et al and assigned to the assignee of the present invention, an alumina/deionized water/hydrogen peroxide slurry was used utilizing a pressure of 10-12 PSI to provide a planarized tungsten-BPSG surface, such that filled vias and a planarized passivation layer were simultaneously formed. See also U.S. Pat. No. 4,702,792 (issued 10/27/87 to Chow et al and assigned to IBM), in which a polymer film is chem-mech polished to define an image pattern.
In the above chem-mech polishing art, the amount of slurry is kept to a minimum. Typically, the slurry is applied by a dropper suspended above the center of the polish wheel. As the wheel spins, the slurry is spread over the polish pad. Examples of low slurry content polishing are shown in U.S. Pat. No. 3,841,031, entitled “Process for Polishing Thin Elements”; U.S. Pat. No. 3,342,652, entitled “Chemical Polishing of A Semi-Conductor Substrate”; U.S. Pat. No. 4,256,535, entitled “Method of Polishing a Semiconductor Wafer”; U.S. Pat. No. 4,373,991, entitled “Method and Apparatus for Polishing A Semiconductor Wafer”; and an article entitled “Spinning Etchant Polishes Flat, Fast” Electronics, Jan. 13, 1982, pp. 40-41.
Use of low slurry content polishing leads to several difficulties. One difficulty is shortened polish pad “lifetime.” Pad lifetime relates to the total number of wafers that can be polished by a given pad. As the pad wears out, both the removal rate of the polished material and the uniformity of removal across the wafer substantially degrade. Pad lifetime is determined by the hardness of the pad, the polish conditions, and the break-in/conditioning procedures. Typically, in order to provide sufficient wetting of a polishing pad used in conjunction with a small amount of slurry, the pad must undergo a destructive break-in procedure (e.g., high-pressure scraping using a blade), as well as periodic conditioning (lower pressure scraping). Such procedures substantially reduce pad lifetime, such that the overall process is more expensive due to the frequency of pad replacement.
Another difficulty is the lack of removal rate uniformity across a given wafer. Using low slurry content processes, the inventors tried to optimize uniformity by changing the slurry content as well as varying the hardness of the pad. None of these changes appreciably enhanced uniformity.
Yet another difficulty is the occurrence of “bumps.” Bumps are areas along the substrate having locally incomplete polishing. Typically they occur over areas that cover steep topologies. For example, when polishing an oxide passivation layer on top of a gate electrode, if the electrode provides a steep “step” (i.e., if it has a height more than approximately 0.5 microns), bumps will tend to form on the portion of the oxide above the edges of the electrode. In low slurry content applications, bumps cannot be eliminated without adversely affecting some other parameter (e.g., rate uniformity, pad life) that needs to be optimized.
Accordingly, there is a need in the art for a planarization process in which both pad lifetime and polish rate uniformity can be maximized while simultaneously minimizing the occurrence of bumps.
SUMMARY OF THE INVENTION
It is thus an object of the invention to provide a chem-mech planarization process that maximizes both pad lifetime and planarization uniformity.
It is another object of the invention to optimize the above parameters while simultaneously minimizing the occurrence of bumps.
It is yet another object of the invention to provide a chem-mech polishing process wherein the need to selectively introduce different slurries is eliminated.
The above and other objects have been met by arranging a retaining wall about the polishing table, and introducing a pool of slurry that completely immerses the polish pad. Moreover, the slurry temperature is raised above room temperature.
By utilizing a polishing process under the above conditions, polish uniformity is in the range of 97%. At the same time, pad lifetime is appreciably extended (up to 10×) because a less vigorous break-in procedure may now be used. Finally, these enhancements do not come at the expense of increased occurrence of bumps; rather, bumps are eliminated.
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Cote William J.
Leach Michael A.
Booth Richard
IBM Corporation
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