Wafer pattern variation of integrated circuit fabrication

Details Wafer pattern variation of integrated circuit fabrication Wafer pattern variation of integrated circuit fabrication

2003-11-03

2004-11-02

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

C257S633000, C438S107000, C438S113000, C438S122000

Reexamination Certificate

active

06812550

ABSTRACT:

BACKGROUND
TECHNICAL FIELD
The present invention relates generally to semiconductor manufacturing technology, and more specifically to wafer temperature control in semiconductor fabrication processes,
BACKGROUND ART
At the present time, electronic products are used in almost every aspect of life, and the heart of these electronic products is the integrated circuit. Integrated circuits are made in and on silicon wafers by extremely complex systems that require the coordination of hundreds or even thousands of precisely controlled processes to produce a finished semiconductor wafer. Each finished semiconductor wafer contains hundreds to tens of thousands of integrated circuits.
Integrated circuits are made up of hundreds to millions of individual components, such as the semiconductor transistor. The most common and important semiconductor technology presently used is silicon-based, and the most preferred silicon-based semiconductor device is a Complementary Metal Oxide Semiconductor (“CMOS”) transistor.
The principal elements of a CMOS transistor generally consist of a silicon substrate having shallow trench oxide isolation regions cordoning off transistor areas. The transistor areas contain polysilicon gates on silicon oxide gates, or gate oxides, over the silicon substrate. The silicon substrate on both sides of the polysilicon gate is slightly doped to become conductive. These lightly doped regions of the silicon substrate are referred to as “shallow source/drain junctions”, which are separated by a channel region beneath the polysilicon gate. A curved silicon oxide or silicon nitride spacer, referred to as a “sidewall spacer”, on the sides of the polysilicon gate, allows deposition of additional doping to form more heavily doped regions of the shallow source/drain junctions, called “deep source/drain junctions”. The shallow and deep source/drain junctions are collectively referred to as “S/D junctions”.
To complete the transistor, a silicon oxide dielectric layer is deposited to cover the polysilicon gate, the curved spacer, and the silicon substrate. To provide electrical connections for the transistor, openings are etched in the silicon oxide dielectric layer to the polysilicon gate and the S/D junctions. The openings are filled with metal to form electrical contacts. To complete the integrated circuits, the contacts are connected to additional levels of wiring in additional levels or layers of interlayer dielectric (“ILD”) material to the outside of the ILD.
These fabrication procedures include a number of thermal processes. The gate oxide layer is thermally grown on the silicon substrate of the semiconductor wafer. The gate oxides and polysilicon gates are also used as masks to form the shallow source/drain regions by ion implantation of boron or phosphorus impurity atoms into the surface of the silicon substrate. The ion implantation is then followed by a high-temperature anneal above 700° C. to activate the implanted impurity atoms to form the shallow source/drain junctions.
A silicon nitride layer is then deposited and etched to form sidewall spacers around the side surfaces of the gate oxides and polysilicon gates. The sidewall spacers, the gate oxides, and the polysilicon gates are used as masks for forming conventional source/drain regions by ion implantation into the surface of the silicon substrate into and through the shallow source/drain junctions. This ion implantation is again followed by a high-temperature anneal above 700° C. to activate the implanted impurity atoms to form the S/D junctions.
As transistors have decreased in size, it has been found that the electrical resistance between the metal contacts and the silicon substrate or the polysilicon has increased to the point that it negatively impacts the performance of the transistors. To lower that electrical resistance, a transition material is formed between the metal contacts and the silicon substrate or the polysilicon. The best transition materials have been found to be cobalt silicide (CoSi
2
) and titanium silicide (TiSi
2
).
The silicides are formed by applying a thin layer of the cobalt or titanium on the silicon substrate above the S/D junctions and the polysilicon gates. The semiconductor wafer hen receives one or more annealing steps at temperatures above 800° C. This causes the cobalt or titanium to selectively react with the silicon and the polysilicon to form the metal silicide.
After the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metalization”, and is performed using a number of different photolithographic and deposition techniques.
One metalization process is called the “damascene” technique, and for multiple layers of channels there is a metalization process called the “dual damascene” technique. These techniques utilize various damascene adhesion, barrier, seed, and conductive materials deposition processes that each require uniform heating of the silicon substrate, usually to high-temperatures.
Such high-temperature deposition and annealing steps present considerable challenges for the fabrication of multiple “dies” or “chips” (regions containing entire integrated circuits) on a single, large semiconductor wafer. During each high-temperature step, temperatures for every die must be the same at every location on the wafer, from edge-to-center-to-edge. Such cross-wafer temperature control is increasingly critical with advances in high-speed semiconductor fabrication processes and the continuing reduction of circuit element dimensions.
Wafer heating uniformity is thus necessary in a great many device fabrication techniques. For example, metal deposition techniques such as physical vapor deposition (“PVD”) or chemical vapor deposition (“CVD”) require a relatively uniform wafer temperature in order to achieve uniform deposition with good adhesion. Still other device fabrication techniques that require uniformity of wafer heating include rapid thermal anneal (“RTA”), temperature gradient zone melting (“TGZM”), lateral epitaxial growth-on-oxide (“LEGO”), and high-temperature recrystallization (“HTR”).
Wafer heating is typically accomplished by placing the wafer on the ends of a number of pins that project from the floor of an oven. A bank of heat lamps is mounted in the upper portion of the oven for heating one of the major surfaces of the wafer. The opposite major wafer surface is exposed to the floor of the oven, which is often cooled by cooling coils or the like. In this arrangement, the opposing major surface of the wafer can be kept cooler than the surface exposed to the heat lamps. This can establish a temperature gradient through the wafer, which is very desirable in achieving TGZM, LEGO and HTR.
However, when the heating is non-uniform across (rather than through) the wafer (“non-uniform lateral heating”) difficulties during wafer processing can occur. For example, during heating of the wafer to accomplish TGZM, temperature variations across the wafer can lead to distortion of the migration pattern of a dopant. Uneven heating during a LEGO process can result in non-uniform melting across the wafer. Lateral temperature variations across the wafer can also result in substantial stresses on the wafer that cause non-elastic deformation (“slip”) of the wafer lattice. Wafer warpage is also caused by such non-uniform lateral heating.
One solution for achieving more uniform wafer heating is to include “dummy” tiles in portions of the wafer where circuits are not being formed. For example, semiconductor dies are usually rectangular but the wafers on which the dies are formed are round. This creates odd-shaped areas at the edge or periphery of the wafer that are too small to be made into a semiconductor die. However, to keep wafer temperatures more uniform, partial die patterns can be fabricated in those areas. Of course, the partial dies are not functional or usable, but they absorb and radiate heat the same as the rest of the

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