Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Reexamination Certificate
1998-10-06
2001-01-09
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
C438S406000
Reexamination Certificate
active
06171931
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wafer of semiconductor material for fabricating integrated devices, and to a process for its fabrication.
2. Discussion of the Related Art
As is known, in the microelectronics industry, the substrate of integrated devices is commonly formed from monocrystalline silicon wafers. In recent years, however, by way of an alternative to all-silicon wafers, so-called SOI (Silicon-on-Insulator) wafers have been proposed. SOI wafers include two layers of silicon, one thinner than the other, separated by a layer of silicon oxide (see, for example, the article entitled: “Silicon-on-Insulator Wafer Bonding-Wafer Thinning Technological Evaluations” by J. Hausman, G. A. Spierings, U. K. P. Bierman and J. A. Pals, Japanese Journal of Applied Physics, Vol. 28, N. 8, August 1989, p. 1426-1443).
FIG. 1
shows a cross section of a portion of a SOI wafer
1
presenting a first (thicker) layer of monocrystalline silicon
2
, an intermediate silicon oxide layer
3
, and a second (thinner) layer of monocrystalline silicon
4
on which an epitaxial layer (not shown) may subsequently be grown. The intermediate oxide layer preferably has a thickness L
1
of 0.2 to 10 &mgr;m.
SOI wafers have recently attracted a good deal of attention on account of the major advantages of integrated circuits with substrates formed from such wafers, as compared with the same circuits with conventional monocrystalline silicon substrates. The advantages may be summed up as follows:
a) higher switching speed;
b) better immunity to noise;
c) low loss currents;
d) no latch-up;
e) reduced stray capacitance;
f) better resistance to radiation; and
g) higher component packing density.
A typical SOI wafer fabrication process will now be described with reference to the
FIG. 2
diagram.
The process commences with two normally fabricated monocrystalline silicon wafers
10
and
11
. Wafer
10
is the one eventually constituting the bottom base layer, and is accurately sized; while wafer
11
is the one which will eventually be thinned and bonded (via the interposition of an oxide layer) to wafer
10
. Wafer
11
(also known as the “bond wafer”) is oxidized thermally to form an oxide layer
12
covering it entirely; and, after being cleaned, wafers
10
and
11
are superimposed and heat treated at 1100° C. for roughly 2 hours to “bond” them together.
During bonding, the following chemical reaction takes place:
≡SiOH+HOSi≡=>≡Si—O—Si≡+H
2
O (1)
wherein the SiOH groups are present in oxide layer
12
; at the heat treatment temperature shown, OH
—
ions are present in oxide layer
12
, to form a strong chemical bond between oxide layer
12
(and hence wafer
11
) and wafer
10
, and so form a semifinished wafer
13
.
Semifinished wafer
13
is then surface ground to form a body
14
, and finally lapped and polished to form wafer
1
.
Despite the major advantages listed above, SOI wafers are of limited application in power circuits on account of the poor thermal conductivity of the silicon oxide layer. Silicon, in fact, is known to present a thermal conductivity of 150 W/(m° C.), as compared with 1.4 W/(m° C.) for silicon oxide (two orders of magnitude lower). As the total thermal resistance of the wafer equals the sum of the thermal resistances of the individual layers (in series with one another), wafer
1
, for a given total thickness, presents a much greater thermal resistance as compared with a traditional monocrystalline silicon wafer. In other words, to achieve the same thermal resistance, silicon layer
2
would have to be thinned by a factor depending on the ratio between the conductivity of silicon oxide and monocrystalline silicon (as shown above, equal to roughly 100) and bearing in mind the thickness of the oxide layer. Such thinning, however, would impair the mechanical strength of the wafer, and is therefore unfeasible, at least for the great majority of applications.
In view of the continual reduction in component size and the need for operating at an increasingly high operating current density, SOI substrates therefore fail to provide for sufficient heat dissipation, thus resulting in excessively high junction temperatures, and impaired reliability of the components. In the case of power components, in particular, a limitation in current flow occurs. Such negative effects are especially damaging in the case of high-voltage integrated circuits requiring thicker intermediate oxide layers. Furthermore, in case of power pulses (e.g. in case of electrostatic discharges), heat cannot be dissipated and locally causes fast increases in temperature.
It is an object of the present invention to provide a wafer which exploits the inherent advantages of SOI technology, but which presents none of the above limitations of application.
SUMMARY OF THE INVENTION
According to the present invention, there are provided a wafer of semiconductor material for fabricating integrated devices, and a process for its fabrication.
In one aspect, the present invention includes a wafer of stacked layers including a first silicon layer, an insulating layer and a second silicon layer. The insulating layer can be formed of silicon carbide, silicon nitride, or a ceramic material, such as beryllium oxide, aluminum nitride, boron nitride and alumina. The insulating layer is formed so that it has a thermal conductivity preferably greater than 10 W/m° K. In another aspect of the invention, a bonding layer is interposed between the insulating layer and the second silicon layer. The bonding layer may be a polycrystalline silicon layer or an oxide layer, such as TEOS oxide, a chemical-vapor-deposited oxide, and a thermally grown oxide. In another aspect of the invention, the insulating layer is formed by thermal deposition in a vacuum chamber on a heated first silicon layer.
REFERENCES:
patent: 4983538 (1991-01-01), Gotou
patent: 5413952 (1995-05-01), Pages et al.
patent: 0 570 321 (1993-11-01), None
patent: 5-160087 (1993-06-01), None
patent: 91 11822 (1991-08-01), None
patent: 93 01617 (1993-01-01), None
Partial European Search Report from European Patent Application 94830577.6, filed Dec. 15, 1994.
Research Disclosure No. 345, Jan. 1993 Havant GB, p. 76 “Wafer-Bonding With Diamond-Like Carbon Films”.
Patent Abstracts of Japan, vol. 11, No. 88 (E-490), Mar. 18, 1987 & JP-A-61 240629 (NEC Corp.).
Mastromatteo Ubaldo
Murari Bruno
Villa Flavio
Dang Trung
Galanthay Theodore E.
Morris James H.
SGS--Thomson Microelectronics S.r.l.
Wolf Greenfield & Sacks P.C.
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