Wafer-mapping method of wafer load port equipment

Details Wafer-mapping method of wafer load port equipment Wafer-mapping method of wafer load port equipment

2000-07-19

2002-09-17

Pyo, Kevin (Department: 2878)

Radiant energy

Photocells; circuits and apparatus

With circuit for evaluating a web, strand, strip, or sheet

C250S559330, C250S559360, C414S936000

Reexamination Certificate

active

06452201

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an operation method of a wafer load port system, and more particularly, to a wafer mapping method of a wafer load port equipment.
2. Description of the Prior Art
Every kind of process equipment is specially designed to meet all sorts of demands in the semiconductor industry. Different parameters are set in various conditions to match process methods and to meet process requirements. Nevertheless, the demand for process stability, uniformity and accuracy is identical. Thus, in different types of process equipment, the semiconductor wafer has to be firmly fixed onto a support brace, and to be placed in a specific process chamber in order to implement every semiconductor process, and to meet the requirement of uniformity and accuracy when considering the pre-designed process parameters.
FIG. 1
shows a wafer carrier in a wafer load port equipment. In tradition, wafer load port equipment
20
is used to uphold a wafer carrier
22
. Thus can the latter be opened or closed. Conventionally, wafer load port equipment
20
entails a support brace
26
in order to connect wafer carrier
22
and to move it to a fixed position of the load port equipment. Support brace
26
entails a bulkhead
24
. The structure of this bulkhead is shown in
FIGS. 1 and 2
. Mating plate
42
is on top of the bulkhead
24
, and this plate is movable. In addition, there is a latch key
54
on the movable mating plate
42
. When the wafer carrier
22
leans on the bulkhead
24
, the door of this carrier faces the direction of bulkhead
24
, and the latch key
54
can be inserted into two holes on the door of the carrier
22
. After the latch key
54
is inserted into the holes, this latch key
54
turns 90 degrees to lock the door of wafer carrier
22
. Furthermore, the plate moves backward, and the wafer carrier
22
can be opened. Mating plate
42
, then, moves downward until a specific position. The above procedures explain how the wafer load port equipment opens the wafer carrier. If the above procedures are conducted in reverse, the opened carrier can be closed.
There are more or less design differences between wafer carriers produced by different manufacturers. Thus, when carriers from different companies are used together, a calibration procedure is required. The load port equipment, afterwards, records the calibration value until the operation of the same procedure next time. That is, while processing calibration, the load port equipment re-records a new value. In addition, it should be noted that this procedure is not only required when using different carriers from different manufacturers, it is also required after the assemblage of the load port equipment.
In conducting the above techniques, sidelong and overlapped issues can be estimated by considering the recorded wafer position, the coordinates and the measurement of the uncertainty volume. If sidelong or overlapped issues do not occur, data acquired by conducting the above techniques can decipher the wafer position with a digital processor. However, the existence of sidelong or overlapped issues can only be determined by a complicated computing process in the above techniques. Thus, it is necessary to accelerate the estimate of these two issues in order to avoid the complicated calculation of wafer mapping developed in the past.
SUMMARY OF THE INVENTION
This invention uses the pattern-based signal to accelerate the evaluation process as a means to replace complicated computing procedures. This invention is constructed through implementing absolute coordinates to produce pattern-based signal by position and two optical sensor signals, and through conducting the feature extraction process. This process produces feature signals of sidelong and overlapped issues. Furthermore, through transforming signals, feature signals can be handled by the digital data processor. Thus, this invention can achieve the three main objectives of wafer mapping.
In summary, the advantage of the wafer-mapping method suggested by this invention is to detect the wafer position, sidelong and overlapped issues through employing the digital-signal method.
It is also the advantage of this invention to rapidly detect the wafer position, sidelong and overlapped issues at the same time.
Using two sensor and position signals in wafer mapping is another advantage of this invention.
Furthermore, this invention is beneficial in conducting the feature extract process through implementing electronic circuits to perform the feature extraction process.
It is still another advantage of this invention to use monolithic microcontroller coupled with software programs to perform the feature extraction process.


REFERENCES:
patent: 6013920 (2000-01-01), Gordon et al.
patent: 6053983 (2000-04-01), Saeki et al.

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