Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2000-11-13
2003-04-22
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S765010
Reexamination Certificate
active
06552527
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a wafer map display apparatus and method for a semiconductor testing device, and more particularly, to a wafer map display apparatus and method which is capable of displaying an entire image of a semiconductor wafer and IC chips therein with an optimal display size within a specified window size even when there is no information available in advance on the number of IC chips or locations of the IC chips on the wafer.
BACKGROUND OF THE INVENTION
A wafer map display apparatus is used in a semiconductor test system for displaying an image of each IC chip on a semiconductor wafer as well as overall characteristics of the wafer for easily and accurately observing the test results. The wafer map display provides important information for evaluating a semiconductor wafer from the standpoint of production yield and quality assurance in a semiconductor production process.
Because a display monitor of a semiconductor test system is usually based on an operating system using “windows”, such a wafer map display is also displayed on the display monitor in a manner similar to other application tools using windows. Therefore, a size of the window for displaying the wafer map is not fixed but frequently changed.
An example of conventional technology involved in such a wafer map display apparatus is explained below with reference to
FIGS. 4 and 5
. First, an entire structure of the semiconductor test system is shown in FIG.
4
. In the example of
FIG. 4
, the system includes a test system main frame, a test station, a wafer prober, a work station WS, a wafer map display application, an input means (key board and mouse, etc.), a storage medium (floppy, hard or other memory disc), and a display device (monitor).
On a semiconductor wafer such as a silicon wafer, a plurality of IC chips to be tested are aligned in a matrix manner. The wafer prober is a handling device that can load, test, and unload semiconductor wafers one by one continuously in combination with the test station of the semiconductor test system. One or more IC chips are tested at the same time by connecting probe pins of the wafer prober to contact pads (electrodes) on the IC chips to establish electrical connection between the IC chips and the semiconductor test system for electrical communication therebetween for the purpose of testing the IC chips.
In the following description, it is assumed that each IC chip is tested one by one for illustration purpose. Thus, during the test, the test result for each IC chip and the X-Y address of the IC chip on the semiconductor wafer are obtained by the semiconductor test system one by one and sent to the work station WS.
The semiconductor test system that is composed of the test system main frame and the test station electronically communicates with the wafer prober through the test station, and tests the IC chips on the semiconductor wafer in a predetermined order. Every time when one IC chip is tested, the semiconductor test system sends the test result (pass/fail) information and category information of the particular IC chip to the work station WS, along with the chip address information of the IC chip on the semiconductor wafer through a communication network or line.
After receiving the test result information (which includes the chip address information on the wafer, pass/fail information in the test result, and the category information) from the semiconductor test system, the work station WS provides the received information to the wafer map display application. The received information is also stored in the storage medium.
The display device is a monitor which displays the test results and other information in a window format. It is rare for the display device used for the wafer map display of such a semiconductor test system that it is set to a single window such as shown in FIG.
5
A. Rather, as shown in
FIG. 5B
, the wafer map display screen is shown on the display device along with other windows of other application tools. Therefore, the window size for the wafer map display varies depending on the size of the other window applications. Moreover, the user can change the window size of the wafer map display through an input means such as a mouse.
In the conventional wafer map display application, the display size for each IC chip is fixed. Because of this, the window size required for displaying an entire semiconductor wafer varies when displaying a wafer of different number of IC chips or a wafer having different XY address alignment of IC chips. An example of a manner of displaying each IC chip is a color display such as using green and red based on the pass/fail information or a color display based on the category information.
An example of wafer map displays in the conventional technology is shown in
FIGS. 5A and 5B
. First, in the example of large window size (window A) in
FIG. 5A
, it displays all of the IC chips within the window A. However, since the display size of each IC chip is fixed, even though the window A of
FIG. 5A
is large enough, the wafer map of the overall semiconductor wafer W is displayed much smaller than the size of the window A. Thus, the display example of
FIG. 5A
has a large portion of unused space, as shown by an area C. In other words, the overall semiconductor wafer is not displayed in the optimal size.
FIG. 5B
shows another display example in the conventional technology in which the display monitor shows windows D, F and G of smaller sizes. The window D shows images of IC chips CH and the semiconductor wafer W wherein not all of the IC chips CH (or entire semiconductor wafer W) are displayed within the window D. Therefore, in this example, the test results of the entire semiconductor wafer is not observed in one screen, and the user has to use a pointing device such as a mouse to scroll the display. Moreover, in this conventional example, it is not possible to easily observe the manner of distribution of characteristics over the entire wafer.
As mentioned above, the conventional wafer map display technology has a drawback in which it is not able to display the IC chips in an optimal size because the chip display size is fixed. Moreover, although the window size required for displaying the entire wafer varies when displaying a wafer of different size, or a wafer of different number of chips or a wafer with different chip alignment, the wafer map display cannot adjust the overall display size of the wafer because the chip display size is fixed. Furthermore, when the window size that displays the wafer map is small, it is burdensome and inconvenient for the user to evaluate the wafer and chips since the entire wafer and all of the chips are not displayed on the monitor.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present intention to provide a wafer map display apparatus and method that is capable of displaying an entire wafer image with an optimal chip display size depending on the number of chips and the XY address information of the chips on the semiconductor wafer relative to the window size in the wafer map display without causing a substantial unused area in the window.
It is another object of the present invention to provide a wafer map display apparatus and method which is capable of calculating and changing an optimal chip display size to display an image of all of the IC chips that have been tested and an overall image of the semiconductor wafer within the specified window size every time when the test result of each IC chip is received from the semiconductor test system.
It is a further object of the present invention to provide a wafer map display apparatus and method of improved test efficiency and accuracy by displaying an image of the IC chips that have been tested with a maximum available size within the specified window size every time when the test result of each IC chip is produced by the semiconductor test system.
To achieve the above objectives, the first aspect of the present invention is a wafer map display apparatus for a semiconductor test system for
Advantest Corp.
Muramatsu & Associates
Nguyen Vinh P.
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