Wafer-level transfer of membranes in semiconductor processing

Details Wafer-level transfer of membranes in semiconductor processing Wafer-level transfer of membranes in semiconductor processing

2001-11-02

2004-08-17

Cuneo, Kamand (Department: 2827)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

With attachment to temporary support or carrier

C438S458000, C438S459000

Reexamination Certificate

active

06777312

ABSTRACT:

ORIGIN OF THE INVENTION
The systems and techniques described herein were made in the performance of work under a NASA contract, and are subject to the provisions of Public Law 96-517 (35 USC 202) in which the Contractor has elected to retain title.
BACKGROUND
This application relates to semiconductor processing, and more specifically, to transfer of a layered structure such as a membrane from one wafer to another wafer.
A semiconductor wafer can be processed to fabricate various structures in an integrated package. Such structures may be formed from fabricating and patterning various layers on the wafer using various microfabrication processes. Each layer may be a semiconductor material, a conductor material such as a doped semiconductor material and a metal, or an insulator such as a glass, an oxide or a nitride. In addition, various micromachining processes may be used to fabricate various micro structures on the wafer. The microfabrication and micromachining processes can be used to fabricate a variety of integrated semiconductor structures to form semiconductor components, devices and systems, including integrated circuits, opto-electronic devices, micro optical devices, and micro-electro-mechanical systems (MEMS).
A layered structure such as a membrane is a common structure in fabricating many semiconductor devices and systems. For example, a silicon or polysilicon membrane parallel to the wafer may be used as an optical mirror. In adaptive optics, such a membrane may be engaged to microactuators to deform in a controlled manner to correct distortions in the wavefront of received optical images. This layered structure may be “natively” grown by directly forming the layer on the wafer on which the final device is fabricated. Alternatively, it may be advantageous or necessary to fabricate such a layer on a separate substrate and then transfer the layer onto the wafer on which the final device is fabricated.
SUMMARY
This application includes techniques for transferring a membrane from one wafer to another wafer to form integrated semiconductor devices. According to one embodiment, a carrier wafer is fabricated to include a membrane on one side of the carrier wafer. The membrane on the carrier wafer is then bond to a surface of a different, device wafer by a plurality of joints. The joints and the device wafer are then isolated from exposure to etching chemicals. Next, the carrier wafer is selectively etched away to expose the membrane and to leave said membrane on the device wafer.


REFERENCES:
patent: 4383886 (1983-05-01), Nakamura et al.
patent: 4700467 (1987-10-01), Donzelli
patent: 4784970 (1988-11-01), Solomon
patent: 4794092 (1988-12-01), Solomon
patent: 5185292 (1993-02-01), VanVonno et al.
patent: 5827755 (1998-10-01), Yonehara et al.
patent: 6004867 (1999-12-01), Kim et al.
patent: 6013534 (2000-01-01), Mountain
patent: 6322903 (2001-11-01), Siniaguine et al.
patent: 6455398 (2002-09-01), Fonstad et al.
patent: 6521477 (2003-02-01), Gooch et al.
Y. T. Chen, “Localized Bonding with PSG or Indium Solder as Intermediate Layer”, 1999 IEEE.*
Michael M. Maharbiz, “Batch Micropackaging by Compression-Bonded Wafer—Wafer Transfer”, 1999 IEEE.*
K.F. Harsh, W. Zhang, V.M. Bright and Y.C. Lee, “Flip-Chip Assembly for Si-Based RF MEMS”, Proc. MEMS '99, Orlando, Florida, pp. 273-278, Jan. 1999.
T. Akiyama, U. Stzufer and N de Rooij, “Wafer-and Piece—Wise Si Tip Transfer Technologies for Applications in Scanning Probe Microscopy”, IEEE Journal of Microelectromechanical Systems, pp. 65-70, 1999.
A. Singh, D.D. Horsley, M. Cohn, A. Pisano and R.T. Howe, “Batch Transfer of Microstructures using Flip-Chip Solder Bonding”, IEEE Journal of Microelectromechanical Systems, pp. 27-33 1999.
H. Nguyen, P. Patterson, H. Toshiyoshi and M.C. Wu, “A Substrate-Independent Wafer Transfer Technique for Surface-Micromachined Devices”, Proc MEMS Conference, 2000.
TE Bell and KD Wise, “A dissolved wafer process using a porous silicon . . . ” Proc MEMS 98, Heidleberg Germany, Jan. 25-29,1998, pp. 251-256.
CG Keller and RT Howe, “Hexile tweezers for teleoperated micro-assembly”, Proc MEMS 97, Nagoya, Japan, 1997 pp. 72-77.

Affiliated with

Also associated with

Rating

Wafer-level transfer of membranes in semiconductor processing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer-level transfer of membranes in semiconductor processing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer-level transfer of membranes in semiconductor processing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3326335