Wafer level system in package and fabrication method thereof

Details Wafer level system in package and fabrication method thereof Wafer level system in package and fabrication method thereof

2011-03-15

2011-03-15

Warren, Matthew E (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S725000, C257S693000, C257SE23062, C257SE23063, C438S202000, C361S783000

Reexamination Certificate

active

07906842

ABSTRACT:
There is provided a system-in-package (SiP), which includes a substrate obtained by cutting a wafer for each unit system; one or more first electronic devices mounted on the substrate by a heat radiation plate; a plurality of interlayer dielectrics sequentially formed on the substrate; and one or more second electronic devices buried between or in the interlayer dielectrics on the substrate. A heat sink may be additionally attached to the bottom surface of the substrate. In this case, a thermal conduction path including heat pipes connecting the heat radiation plate on the substrate and the heat sink is formed. In the SiP, various types of devices are buried at a wafer level, so that a more integrated semiconductor device is implemented corresponding to demand for a fine pitch. Further, the heat radiation of a device required in high-speed operation and high heat generation is maximized due to the multi-stepped heat radiation structure, and thus the operation of the device is more stabilized.

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patent: 2004/0125579 (2004-07-01), Konishi et al.
patent: 2005/0151240 (2005-07-01), Takeda et al.
patent: 2006/0214288 (2006-09-01), Ohsumi

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