Wafer level stacked package

Details Wafer level stacked package Wafer level stacked package

2007-01-30

2007-01-30

Williams, Alexander Oscar (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257SE23061, C257SE23125, C257SE23005, C257SE23008, C257SE23026, C257SE23067, C257SE23013, C257SE23105, C257SE25023, C257S686000, C257S685000, C257S723000, C257S778000, C257S737000, C257S738000, C257S698000

Reexamination Certificate

active

11128633

ABSTRACT:
Disclosed are a wafer level stacked package and its manufacturing method. As one example, in such a wafer level stacked package, a first semiconductor die is electrically connected to an upper surface of a substrate and a second semiconductor die is electrically connected to a lower surface of the substrate. That is, with respect to one substrate, semiconductor dies can be stacked on upper and lower surfaces of the substrate. Also, underfill is formed between the respective semiconductor dies and the substrate, thereby enhancing bonding forces between the respective semiconductor dies and the substrate. In addition to stacking the semiconductor dies, packages can be stacked with each other. That is, it is possible to stack a plurality of completed wafer level packages with each other in an up-and-down direction.

REFERENCES:
patent: 6493240 (2002-12-01), Broglia et al.
patent: 6815712 (2004-11-01), Kline
patent: 6835895 (2004-12-01), Asai et al.
patent: 6876088 (2005-04-01), Harvey
patent: 6906415 (2005-06-01), Jiang et al.
patent: 6949407 (2005-09-01), Jeung et al.
patent: 2002/0031864 (2002-03-01), Ball
patent: 2003/0042587 (2003-03-01), Lee
patent: 2003/0089978 (2003-05-01), Miyamoto et al.
patent: 2003/0138993 (2003-07-01), Nakamura et al.
patent: 2003/0232462 (2003-12-01), Poo et al.
patent: 2004/0012078 (2004-01-01), Hortaleza
patent: 2004/0104469 (2004-06-01), Yagi et al.
patent: 2004/0178514 (2004-09-01), Lee et al.
patent: 2006/0006521 (2006-01-01), Boon et al.
patent: 2006/0043603 (2006-03-01), Ranade et al.

Affiliated with

Also associated with

Rating

Wafer level stacked package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer level stacked package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer level stacked package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3723156