Wafer-level solder bumps

Details Wafer-level solder bumps Wafer-level solder bumps

2007-06-26

2009-08-18

Potter, Roy K (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S778000

Reexamination Certificate

active

07576434

ABSTRACT:
In one embodiment, the present invention includes a semiconductor package having a support substrate coupled to a first semiconductor die, where the first semiconductor die includes first conductive bumps, and a second semiconductor die includes second conductive bumps, and where the first and second die are coupled by joints formed of the first and second conductive bumps and a solder material therebetween. Other embodiments are described and claimed.

REFERENCES:
patent: 6340845 (2002-01-01), Oda
patent: 7279795 (2007-10-01), Periaman et al.
patent: 7352067 (2008-04-01), Fukaishi et al.
U.S. Appl. No. 11/321,669, filed Dec. 29, 2005, entitled, “A Stacked Die Semiconductor Package,” by Shanggar Periaman, et al.

Affiliated with

Also associated with

Rating

Wafer-level solder bumps does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer-level solder bumps, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer-level solder bumps will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4091825