Wafer level reliability contact test structure and method

Details Wafer level reliability contact test structure and method Wafer level reliability contact test structure and method

1992-02-24

1993-08-24

Wieder, Kenneth A.

Electricity: measuring and testing

Impedance, admittance or other quantities representative of...

Lumped type parameters

324500, 324158R, 324158T, G01R 3126

Patent

active

052392708

ABSTRACT:
A contact test structure and method provide accelerated testing of long term reliability of metal to silicon ohmic contacts and adjacent PN junctions on IC dies of a wafer. At least one wafer level reliability contact test structure (10) is formed on the wafer during CMOS or BICMOS wafer fabrication mask sequences without additional steps. A shallow layer (N+S/D) of semiconductor silicon material of second type carrier (N) conductivity is formed in a well (PWELL) of first type carrier (P) conductivity silicon material with a shallow PN junction (J) between the shallow layer and well. Metal to silicon first and second test contacts (TC1,TC2) of metal layer portions (M1) are formed at first and second locations on the shallow layer (N+S/D) spaced apart a selected distance. The second test contact (TC2) has a contact area between a metal layer (M1) and shallow layer (N+S/D) in the minimum size range for the fabrication process for maximizing current density through the second test contact (TC2). The first test contact (TC1) has a substantially greater contact area. A large current is forced in a conductive path through the shallow layer (N+S/D) between the first and second test contacts (TC1,TC2). Changes in the resistance of the conductive path caused by changes in the contact resistance of the second test contact TC2 over time are monitored as a function of applied first and second voltages (V1,V2) and forced current. Additional contact test structure is formed on the well with an ohmic contact layer (P+S/D) spaced from the shallow layer (N+S/D) and metal to silicon third test contact (TC3) to detect occurrence of junction spiking.

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