Wafer level production of chip size semiconductor packages

Details Wafer level production of chip size semiconductor packages Wafer level production of chip size semiconductor packages

2000-09-05

2002-06-18

Le, Vu A. (Department: 2824)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S118000, C438S122000, C438S123000, C438S124000, C438S192000, C438S460000

Reexamination Certificate

active

06406934

ABSTRACT:

BACKGROUND
1. Technical Field
This invention pertains to semiconductor packaging in general, and in particular, to making chip size semiconductor packages (“CSPs”) that require no encapsulation or interconnective substrate.
2. Related Art
The increasing demand for electronic devices that are smaller, lighter, and yet more functional has resulted in a concomitant demand for semiconductor packages that have smaller outlines and mounting footprints, yet which are capable of increased component packaging densities. One response to this demand has been the development of so-called chip-scale, or chip-size, semiconductor packages (“CSPs”) having outline and mounting (“O&M”) dimensions that are only slightly greater than those of the semiconductor die, or “chip,” packaged therein.
FIGS. 1 and 2
are respectively a top plan and a cross-sectional side elevation view of a semiconductor package
110
incorporating a substrate
112
and a semiconductor die
114
having an integrated circuit (“IC”) mounted on it in accordance with the prior art. The substrate
112
illustrated comprises a layer
120
of an insulative material, e.g., a polyimide resin film, laminated between top and bottom conductive layers
122
,
124
of a metal, e.g., copper or aluminum. The conductive layers
122
,
124
are patterned to define wire bonding pads
126
and circuit traces
128
in the top layer
122
, and circuit traces
128
and solder ball mounting lands
130
in the bottom layer
124
. The terminal pads
126
and circuit traces
128
are connected to the solder ball lands
130
through the substrate
112
by “vias”
132
, i.e., plated-through holes. The solder balls
118
mounted on the lands
130
serve as the input/output terminals of the package
110
.
The die
114
has input/output wire bonding pads
134
located at the peripheral edges of its respective top, or “active,” surface, and is attached to the top surface of the substrate
112
with, e.g., a layer
136
of an adhesive or an adhesive film. The die pads
134
are then wire bonded to the substrate pads
126
with fine, conductive wires
138
, typically gold or aluminum. After wire bonding, the substrate
112
, the die
114
, and the wires
138
are “overmolded” with a dense, monolithic body, or “mold cap”
144
(shown by dotted outline in
FIG. 2
, omitted for clarity in FIG.
1
), of plastic, typically a filled epoxy resin, that encapsulates the packaged parts and protects them from environmental elements, particularly moisture.
It may be seen that the size, cost and complexity of the prior art CSP
110
can be reduced considerably if the substrate
112
and the encapsulating mold cap
114
, along with the manufacturing processes associated with them are eliminated.
BRIEF SUMMARY
This invention provides a manufacturing process for making chip-size semiconductor packages (“CSPs”) at the wafer level that eliminates the added size, expense, and complexity of an interconnective substrate, such as a laminate or a lead frame, as well as the need to encapsulate the package in a plastic body.
One embodiment of the method includes the provision of a semiconductor wafer having a plurality of semiconductor dies formed integrally therein. Each die has opposite top and bottom surfaces and an electronic integrated circuit (“IC”) device formed in the top surface thereof. One or more conventional device input-output terminal pads are located on the top surface of each die and are electrically connected internally to the electronic device therein.
A via having interior walls is formed through the dies and each terminal pad thereon. In one advantageous embodiment, the vias are ablatively formed through the dies and terminal pads with a laser, and at a temperature high enough to form an insulative coating on the interior walls of the vias simultaneously with the formation of the vias.
Metallizations are formed in the vias and on the bottom surfaces of the dies that redistribute the input-output signals of the IC devices from the terminal pads on the top surfaces of the respective dies, through the vias, and to an array of input-output pads, or lands, on the bottom surface of the respective dies. An optional protective coating may be formed on one or both of the upper and lower surfaces of the wafer to protect against, e.g., moisture.
When processing of the wafer is complete, the resulting “packaged” dies are separated, from the wafer, e.g., by sawing, and are ready for immediate attachment to an associated PCB without requiring an interconnective substrate or overmolding. However, if desired, the dies may be soldered to a substrate and encapsulated along the lines of the prior art package shown in
FIGS. 2 and 3
.
A better understanding of the above and other features and advantages of the present invention may be had from a consideration of the detailed description below of some exemplary embodiments thereof, particularly if such consideration is made in conjunction with the appended drawings.


REFERENCES:
patent: 5229647 (1993-07-01), Gnadinger
patent: 5506756 (1996-04-01), Haley
patent: 5682062 (1997-10-01), Gaul
patent: 5858815 (1999-01-01), Heo et al.
patent: 5863813 (1999-01-01), Dando
patent: 5888884 (1999-03-01), Wojnarowski
patent: 5933711 (1999-08-01), Cho
patent: 5977624 (1999-11-01), Heo et al.
patent: 6002163 (1999-12-01), Wojnarowski

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