Wafer-level processing of chip-packaging compositions...

Details Wafer-level processing of chip-packaging compositions... Wafer-level processing of chip-packaging compositions...

2008-01-01

2008-01-01

Nhu, Daivd (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S112000, C438S124000, C257SE21502, C257SE21503

Reexamination Certificate

active

07314778

ABSTRACT:
A process of packaging a microelectronic chip includes wafer-level application of a chip-packaging composition that includes a polymer of a bis-maleimide. A process includes wafer-level addition of the chip-packaging compositions that include adding particulate fillers to achieve a coefficient of thermal expansion of about 20 ppm/K. A computing system is also included that uses a microelectronic die that was processed with the bis-maleimide at the wafer level, before singulation.

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Jayaraman, S., et al., “Chip-Packaging Compositions, IncludingBis-Maleimides, Packages Made Therewith, and Methods of Assembling Same”,U.S. Appl. No. 11/323,475, filed Dec. 30, 2005), 52 pgs.
Vo, H. T., “Towards Model-Based Engineering of Underfill Materials: CTE Modeling”,Microelectronics Journal, 32(4), (Apr. 1, 2001), 331-338.

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