Wafer level packaging technique for microdevices

Details Wafer level packaging technique for microdevices Wafer level packaging technique for microdevices

2006-11-21

2006-11-21

Tsai, H. Jey (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S118000, C438S121000, C438S051000

Reexamination Certificate

active

07138293

ABSTRACT:
A method is disclosed for fabricating a integrated device, such as a MEMS device. A first wafer is provided on an exposed surface with a layer of gold, gold alloy or gold compound. A second wafer is provided on its exposed surface with under-layer of gold, gold alloy or gold compound; and an over- of bismuth, bismuth alloy, a compound of bismuth, cadmium, cadmium alloy, a compound of cadmium compound, tin, tin alloy, or a compound of tin. The wafers are then brought into contact and bonded at their surfaces through the deposited layers.

REFERENCES:
patent: 2002/0071169 (2002-06-01), Bowers et al.
patent: 2002/0096421 (2002-07-01), Cohn et al.
patent: 2002/0179986 (2002-12-01), Orcutt et al.
patent: 2003/0116845 (2003-06-01), Bojkov et al.
patent: 2003/0151479 (2003-08-01), Stafford et al.
patent: WO 01/98786 (2001-12-01), None
patent: WO 02/42716 (2002-05-01), None

Affiliated with

Also associated with

Rating

Wafer level packaging technique for microdevices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wafer level packaging technique for microdevices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wafer level packaging technique for microdevices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3643018