Wafer level packaging process

Details Wafer level packaging process Wafer level packaging process

2005-11-03

2008-07-01

Dang, Phuc T. (Department: 2892)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

C257S684000, C450S003000

Reexamination Certificate

active

07393758

ABSTRACT:
Wafer level packaging process for packaging MEMS or other devices. In some embodiments, a MEMS wafer with normal thickness is firstly bonded to a cap wafer of normal thickness, followed by a thinning on the backside of the MEMS wafer. After this, the bonded wafer stack and the capping of the hermetically packaged MEMS devices are still rigid enough to do further processing. On this basis, through vias on the thinned substrate can be easily formed and stopped on the regions to be led out (e.g., metal pads/electrodes, highly doped silicon, etc.). Vias can be partially filled as this is the final surface of process. Even thick metal coated/patterned vias have much more space to relax possible thermal stress, as long as the vias are not completely filled with hard metal(s). Various embodiments are disclosed.

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